Post by: John123 on April 01, 2020, 02:01:30 PM
Are there trade offs with the fast recovery versions in general other than cost?
Post by: davekni on April 01, 2020, 08:47:11 PM
Post by: John123 on April 02, 2020, 11:32:19 AM
My thinking with the fast recovery diode version is it'll cope better with high dv/dt turn off pulses. Its to replace a fet in a project which has much higher parasitic input capacitances and is a bit too close to switching back on again under heavy load, I'm thinking 3v gs threshold might help with that too since the current 2v gs-th SIHG73N60E almost couples that back onto its gate during the high dv/dt events.
It's a good mosfet and actually cost me quite a bit of change back in 2014, but I can repurpose it. I've been looking on RS components and hadn't realized how far MOSFET technology has come over the last few years. The high input capacitances of the SIHG73N60E have more than halved. Fets with fast recovery diodes are new to me too :D
Post by: davekni on April 02, 2020, 08:09:29 PM
Yes, I never rely on avalanche ratings either. However, my limited and unscientific observations would suggest that parts with higher avalanche ratings tend to be more robust. Perhaps that's due to occasional unintended over-voltage spikes during startup current peaks combined with parasitic wiring inductances. The reduction with SIHG039N60EF is small, so I'd take the fast diode over the small avalanche energy difference.
That does look like a very nice FET you've found. That's certainly one I'll consider if designing another high-power FET circuit. The only caution I have is that the low Crss makes for very rapid slew rate on Vds. I have some 200V FETs with similar on-resistance and low Crss. They kept frying in an H-Bridge design with transformer-coupled gate drive because the high slew rate produced gate currents due to winding-to-winding capacitance that were so high frequency that the leakage inductance of the transformer wasn't low enough to shunt them. That feedback caused a couple cycles of very-high frequency full-amplitude oscillation at each intended H-Bridge switching point.
Post by: johnf on April 02, 2020, 08:24:07 PM
speed isn't everything the enemy of electroncs is dv/dT and di/dt.
Super fast switching leads to emi issues that can be extremely hard to mitigate
The perfect FET has still to be produced but we now have more options
Post by: T3sl4co1l on April 04, 2020, 09:01:32 AM
Max dV/dt is a different parameter, and for that matter, usually hard to exceed without mixing technologies (e.g., you might stress a Si FET with the speed of a SiC or GaN FET).
Avalanche and recovery are indeed in a tradeoff, something to do with minority carriers and their distribution. Avalanche is best not to rely on in the first place. Occasional light loading might be fine, but there are few applications where that even comes up, and repetitive full-load avalanche such as a poorly-wired inverter would experience, will quickly lead to destruction.
Tim
Post by: John123 on April 06, 2020, 07:49:30 PM
Post by: John123 on April 08, 2020, 11:40:04 PM
Is this likely to cause problems when used as a drop in replacement? Lets say my max peak primary current is around 27 amps at high powers, well that seems like its got a lot of potential to swing back around and exceed 14.4 amps, or am I off base here?
Edit: hmm swapped it out and there's a ton of ringing at turn off, does the lower gate capacitance mean I should increase the gate resistor to compensate?
Post by: T3sl4co1l on April 09, 2020, 05:10:31 AM
Tim
Post by: John123 on April 09, 2020, 05:32:41 AM
Post by: davekni on April 09, 2020, 05:47:51 AM
If this is a boost-converter type circuit without resonant capacitor, the FET body diode typically never conducts, as there is never reverse drain-source current flowing.
Post by: John123 on April 09, 2020, 06:33:52 AM
Regarding the ringing I mentioned, it appears that having a ferrite bead on the source pin can actually make things worse. I'd already got them on the gate and drain legs but thought I'd add one to the source when I swapped the fet out, but now I've removed it again the turn off is much cleaner (under load). This was also scoping right at the body with the probes bypassing the beads.
There's still the foundation of something there, right as the fet hits the 3vgs threshold voltage at turn off.
Post by: T3sl4co1l on April 10, 2020, 06:59:00 AM
But it is a hard switched flyback topology I'm using, but it doesn't matter then?
You gave absolutely no context so I assume the default, a half bridge Tesla Coil or something like that.
Hard switched flyback, forces recovery of the secondary diode.
If you're working with this circuit,
https://highvoltageforum.net/index.php?topic=1007.0
it is also not hard switched, with no diode shown and a snubber provided.
Flybacks are usually driven in quasi-resonant as mentioned above.
Tim
Post by: John123 on April 10, 2020, 07:43:03 AM
First impressions of the new fet and it would appear that it runs a bit cooler without any tweaks.
Post by: davekni on April 11, 2020, 01:00:48 AM
Thank you for sharing the circuit! That's an interesting variation on a resonant flyback. What I'm used to seeing is w/o the diodes nor 1.5uH inductor, with the right side of the 220nF capacitor connected to either ground or the +30V supply.
This version has one key advantage: It will start cleanly if +30V is supplied first and then +18V. If a normal resonant flyback is started in that sequence, the FET will charge the resonant capacitor (220nF) during it's first gate pulse, dissipating 0.5*C*V*V internally, and with high initial peak FET current. This can fry the FET on startup if supplies are sequenced with drain voltage before gate.
The disadvantage is that the FET Vds rises rapidly for the initial 30V until the upper diode conducts (and a bit farther due to the diode's forward recovery time and parasitic inductances). It doesn't rise to peak voltage immediately like a non-resonant circuit would, so is a compromise, semi-hard switching for the off-transition.
The FETs internal body diode is soft-switched as in normal resonant flyback circuits.
BTW, this interesting circuit prompted me to run quick simulations to make sure I was understanding it's operation correctly.
Post by: John123 on April 11, 2020, 01:24:46 AM
Type "non dissipative snubber" into google images you'll get some results for this arrangement, you're right it's like a best of both worlds sort of thing. You don't get that true LC resonance ringing back and forth like on some single ended drivers, so the transistor isn't subjected to those "untimed and untuned rings" if that makes sense. Without feedback to time the pulses the transistor can often turn on at the wrong moment and shunt the contents of the resonant cap, at least that's what I think sometimes happens in those single ended 555 drivers.
I've got a few changes on mine however:
100nF instead of 220nF, helps get bigger arcs with lower supply voltages and smaller flybacks.
SIHG039N60EF 600v fet for the reason above, although a 400v one would be more than adequate. I was just going for a lot of extra headroom, 200v fets however were not enough in my experiments as that's around the level where things start getting good (unless you've got a monster flyback with really high turns ratio).
Soon a TVS string across the drain and source, just incase!
High impedance RCD snubber across the primary coil for measuring peak voltages with a DC voltmeter (UF4007 4.7nF 10 Megaohm), I think it may actually help with the disadvantage you noted as it's a little more stable when producing large arcs with it included. I only found this out by accident, originally the 10 megohm was my multimeter input impedance and when I removed it would change the stability of the arc (when making 5cm+ arcs).
The disadvantage is that the FET Vds rises rapidly for the initial 30V until the upper diode conducts (and a bit farther due to the diode's forward recovery time and parasitic inductances). It doesn't rise to peak voltage immediately like a non-resonant circuit would, so is a compromise, semi-hard switching for the off-transition.
10 ohm resistor in series with the gate turn off diode, without made the circuit go haywire with the previous fet (probably parasitic inductance and capacitance related).
UCC28C45 instead of UC3844, has lower UVLO and is a modern drop in replacement version, but I didn't really notice any difference other than it works from 12v.
18v zener on the gate.
1 amp schottky diode from ground to pin 6 as recommended in the UC384x datasheets.
RC snubbers across the lossless snubber diodes, I went crazy trying to get a clean current sense signal.
1nF+1.2k for the current sense RC filter, I think this is where I went wrong but its all I had at the time. 1k + 470pF seems common online for this IC, could mine be too large?
What do you use for simulations? I could do with some kind of simulator myself for this sort of thing.
Post by: davekni on April 11, 2020, 04:47:39 AM
The big advantage of UCC28C45 or similar chips over 555 is current sensing. This fixes issues of accidentally setting too long a FET on-time, and partially-fixes issues of too short a FET off-time. If the off-time is too short, the FET turns-on with high Vds. The UCC28C45 current sense will shut it off, hopefully before the FET fries. If this continues for many cycles, however, the FET may still eventually fry. That's the biggest issues with your 1.2us long current-sense filter. It slows down response to short off-time high-current conditi9ons.
Changing 220nF to 100nF should make your primary and secondary peak voltages higher. Going too low can hurt performance, however, if the primary resonance is too fast for the secondary to track due to its parasitic winding capacitance.
There are several free analog simulators available. The one I prefer (and have been using for 20+ years at home and work) is LTSpice (also sometimes called SwitcherCad). It's from Linear Technology, which was purchased by Analog Devices. The standard documentation is a bit basic, but there's lots of great information on user groups etc. LTSpice has all sorts of shortcuts and features that aren't formally documented, but that are very useful, such as plotting power dissipation of parts (alt-left-click to probe). I'd be happy to send my simulation file if you are interested. (I'll try attaching it, but that likely won't work, so send me an email at davekni@yahoo.com.)
[ Invalid Attachment ]
I included my local FET library file as well. That isn't necessary if you change the FET to something in LTSpice's standard library. (There's an independent program called MOSTool for taking data-sheet parameters and converting them into LTSpice FET models. That's where all the FETs in the attached library come from.)
Post by: SteveN87 on April 11, 2020, 01:25:10 PM
Quote
f the off-time is too short, the FET turns-on with high Vds.
My 1990's ignition coil driver attempted to address that with crude voltage sensing:
[ Invalid Attachment ]
It's basically a transistorised Ruhmkorff coil. Q1 defaults to ON, the primary current builds up until there's about 0.7 V across R4, then Q2 starts to pull the FET gate down. At some point, the drain voltage will start to rise and C1 will accelerate the turn off of Q1, keeping it off until the drain voltage returns to a low value. Q2 eventally turns off and the cycle repeats. C1 and R3 also form an RC snubber.
Such a simple circuit obviously has limitations: e.g. the gate drive waveform is awful and hold-off action diminishes with increased output loading.
Edit: A simulation of this shows that it doesn't do a very good job of holding off until Vds drops to an acceptably low value. There are conflicting requirements for the snubber action on the hold-off action. Good snubbing = poor hold-off. The MK2 version will separate the two functions...
Post by: John123 on April 13, 2020, 11:53:36 AM
Adding the TVS diodes may help the same issue as the RCD snubbing was helping. Either solution is to handle parasitic inductance. Even the normal flyback could need snubbing if parasitic inductance is high. The extra diode in this circuit just adds a bit to parasitic inductance. At FET turn-off, the FET current suddenly transfers to a path through the 100nF cap, diode, and bypass capacitance from +30V back to ground. (The current-sense resistors are also in the parasitic-inductance loop, as the current stops through them.) So, that entire path needs to be low inductance, short connections ideally as copper against a ground plane. For most such circuits, I either cut gaps in one side of two-sided copper-clad board to make circuit nodes, or apply copper tape to a thin dielectric (phenolic or mylar) - ground on one side and interconnect sections on the other side.
The big advantage of UCC28C45 or similar chips over 555 is current sensing. This fixes issues of accidentally setting too long a FET on-time, and partially-fixes issues of too short a FET off-time. If the off-time is too short, the FET turns-on with high Vds. The UCC28C45 current sense will shut it off, hopefully before the FET fries. If this continues for many cycles, however, the FET may still eventually fry. That's the biggest issues with your 1.2us long current-sense filter. It slows down response to short off-time high-current conditi9ons.
Changing 220nF to 100nF should make your primary and secondary peak voltages higher. Going too low can hurt performance, however, if the primary resonance is too fast for the secondary to track due to its parasitic winding capacitance.
There are several free analog simulators available. The one I prefer (and have been using for 20+ years at home and work) is LTSpice (also sometimes called SwitcherCad). It's from Linear Technology, which was purchased by Analog Devices. The standard documentation is a bit basic, but there's lots of great information on user groups etc. LTSpice has all sorts of shortcuts and features that aren't formally documented, but that are very useful, such as plotting power dissipation of parts (alt-left-click to probe). I'd be happy to send my simulation file if you are interested. (I'll try attaching it, but that likely won't work, so send me an email at davekni@yahoo.com.)flyback.zip
I included my local FET library file as well. That isn't necessary if you change the FET to something in LTSpice's standard library. (There's an independent program called MOSTool for taking data-sheet parameters and converting them into LTSpice FET models. That's where all the FETs in the attached library come from.)
Wow thanks Dave! The simulation file works fine, been having a play with it.
I did notice reduced performance with less snubbing capacitance with that other driver I've been messing with, it switches much slower anyway but going below 47nF makes the output power diminish. Like the voltage might get a tad higher but it goes really weak and spindly.
Yeah I'll swap out the RC filter for one with a lower time constant then.
When there's a current sense resistor in series with the fet source pin should the TVS go from drain-ground or drain-source (same goes for that snubber inductor), the simulation would appear to suggest the position of the snubber inductors low end doesn't really matter. But that doesn't take into account parsitics.
Quotef the off-time is too short, the FET turns-on with high Vds.
My 1990's ignition coil driver attempted to address that with crude voltage sensing:
[ Invalid Attachment ]
It's basically a transistorised Ruhmkorff coil. Q1 defaults to ON, the primary current builds up until there's about 0.7 V across R4, then Q2 starts to pull the FET gate down. At some point, the drain voltage will start to rise and C1 will accelerate the turn off of Q1, keeping it off until the drain voltage returns to a low value. Q2 eventally turns off and the cycle repeats. C1 and R3 also form an RC snubber.
Such a simple circuit obviously has limitations: e.g. the gate drive waveform is awful and hold-off action diminishes with increased output loading.
Edit: A simulation of this shows that it doesn't do a very good job of holding off until Vds drops to an acceptably low value. There are conflicting requirements for the snubber action on the hold-off action. Good snubbing = poor hold-off. The MK2 version will separate the two functions...
What about a seperate snubber, could that perhaps solve the hold off problem?
Post by: SteveN87 on April 13, 2020, 12:57:56 PM
Quote
What about a seperate snubber, could that perhaps solve the hold off problem?
Yes - it does. The MK2 version is looking good on the simulator. I'm using @davekni's resonant rise and your filtered current sense signal suggestions (many thanks to you both). The hold off now takes the form of a very long off time that gets cancelled by the zero crossing of the drain/collector voltage. The gate drive waveform has been improved too.
Post by: davekni on April 14, 2020, 06:02:54 AM
Too low a flyback resonant capacitor can make the primary waveform too fast for the secondary to follow, given the secondary's parasitic winding capacitance. The primary ends up resonating more with the transformer's leakage inductance, with little energy transferring to the secondary.
Glad that LTSpice is working well for you!
Post by: John123 on April 14, 2020, 03:46:06 PM
The files are downloaded here https://www.vishay.com/mosfets/list/product-92209/tab/designtools-ppg/ (https://www.vishay.com/mosfets/list/product-92209/tab/designtools-ppg/) but it comes in a .zip form and doesn't make much sense :(
I've tried watching a few youtube tutorials but they don't appear to work.
Edit: I think I got it by opening the .lib file in ltspice and right clicking on the .subckt part and creating symbol, then it appears in auto generated when adding a new component. But the symbol looks weird and not like other MOSFETs in the program.
But now the simulations are taking ages to run.
Anyway I was trying to simulate what would happen if the controller IC in the circuit I posted was swapped for the 99% max duty cycle type, is the fet likely to go pop if the snubber hasn't had enough time to do its thing?
Post by: davekni on April 14, 2020, 10:10:44 PM
LTSpice actually has a unique internal model for power MOSFETs that they call VDMOS. It's very efficient for simulation and usually good enough for most purposes. (In certain cases where lead inductance is critical, I add external inductors to simulate that.) All the FETs in the library file I sent are using that internal model. LTSpice comes with many included device models as well. Usually searching down that list will reveal one close enough for basic simulations. Right-click on the NMOS part in your schematic, select "Pick New MOSFET", then scroll through the list and/or sort by parameter.
There was (and perhaps is) a tool for building VDMOS models. It lived within yahoo groups, which has gone away. Hopefully the tool is archived somewhere else. I have it on my work computer (inaccessible at the moment), and used it to generate all the models in the library file I'd sent you. If I can find a link to the tool, I'll share it.
Post by: John123 on April 15, 2020, 03:32:37 PM
Back to the circuit for a moment, would switching to the 100% max duty cycle version of the chip likely cause blown silicon? I'm thinking for lower primary voltages like 12v it might help produce more output voltage with some more stubborn flybacks without having to drop the frequency into the hearing range, the simulation would suggest there's more room for play to about 75% but just wanted to be sure before I blow something.
How critical is the off time vs on time?
Edit: Tried a KA3843 and it would appear the 50% duty cycle limit is needed for general purpose use, I was able to crank the power up using the 100% (95% actual) max chip up until a certain point where the output from the flyback would vanish and current draw would remain high. Shame they don't make a chip with a 70% limit as that's where it drops off.
But there was definitely gains to be made across the board, near the hearing range arcs could start at a much larger distance whilst at higher frequencies arcs were thicker and could be stretched out further. Overall the circuit appears to be a lot more noisy and screechy so I'm guessing keeping it below the critical duty cycle operating point is no trivial task with a load such as an arc.
Edit2: Tried another flyback and it appears to have another runaway mode at higher duty cycle setpoints, arcs keep going but the current disproportionately shoots up without having anything to show for it on the output.
Edit3: Tried that useless monitor flyback its just as useless regardless! ::)
Post by: davekni on April 15, 2020, 10:16:53 PM
First, the simulation file has a line ".inc fet.lib" on the schematic. As long as the file "fet.lib" is in the same directory as the circuit, it will be read in. (A full path can be used for the ".inc" command.)
There may be more GUI methods to select parts from a user library, but I use the crude text options. Either right-click on the part-name text of the FET, or cntl-right-click on the FET symbol body. Then type in one of the parts in the library. (I edit the fet.lib file using a text editor, but I gather you can do that within LTSpice.)
For normal flyback operation (not drawing arcs), the necessary minimum off-time is the half-cycle time of the primary LC resonance (transformer primary L and resonant C, 100nF in your case). For TVs, this is usually 10-20% of the period (80-90% on-time). The minimum off-time is a fixed time value (defined by L and C), not a fixed duty-cycle value. Minimum off-time of KA3843 is determined by oscillator capacitor value and internal pull-down current. See figure 6 in the spec. If you pick a capacitor to get the correct off-time (dead-time) for a given flyback and resonant capacitor, you can adjust frequency by changing the oscillator R. The R value has little effect on dead-time. (Can you scope the flyback primary to see the resonant half-cycle time?)
When drawing arcs, the waveform gets messy, some combination of the normal resonance and the higher-frequency resonance of flyback leakage inductance. The above dead-time may still work reasonably well. A fancier option would be to detect the voltage across the resonant capacitor, and extend the dead-time until resonant capacitor voltage is back close to zero.
Yes, too short a dead-time is likely to fry the FET, as the FET is discharging the resonant cap directly, resulting in very-high inrush current.
Monitor flybacks typically run at much higher frequencies, which makes handling secondary winding capacitance tricky. My guess is that such flybacks are carefully tuned for a specific resonant capacitance and frequency that works will with the secondary resonances.
Post by: John123 on April 16, 2020, 07:44:54 AM
I might be able to scope the drain whilst running at lower powers, I've only got a x10 300v probe so don't want to risk damaging the scope. My worry is at startup there could be tranistants exceeding this.
I've been reading online and found I might need something called slope compensation to make it more stable at >50% duty cycles, not sure if that's suited to the current schematic however. One method used a resistor from the timing cap to current sense pin whilst another used a signal transistor along with the resistor. Another said to put a signal diode between the gate drive output to current sensing pin.
Post by: davekni on April 16, 2020, 07:28:59 PM
Looking KA3843 spec. figure 6, the 3.3nF on KA3843-4 in the schematic you shared would result in a bit less than 1us dead-time, which may appear as roughly 0. (I'm presuming you meant all the way to 0% dead time, not 0% duty cycle.) The flyback half-cycle time is likely around 10us, which requires 47nF from pin 4 to ground. The 22k POT will need to drop to 1-2k to get reasonable frequency range with 47nF.
At higher frequencies (low POT values), the dead-time will increase some even with a constant capacitor value, as the POT's pull-up current is competing with the KA3843's internal 6.3mA pull-down current.
For this flyback use, I don't think slope compensation is needed. Slope compensation is needed for continuous current-mode switchers, where the current increases during the on-time and decreases during the off-time, but not to zero. In this situation, slope-compensation avoids sub-harmonic oscillations (on-time varying in a cyclic pattern over many cycles). The biggest issue with sub-harmonic oscillations is audible noise, not parts frying.
For probing, yes, 300V may not be enough probe capability. One easy solution in this case is to lay the probe near the FET drain but not touching, or wrap a small bit of insulated wire around the probe end and connect that wire to the drain. This gets enough of the AC signal to see the flyback half-cycle time. The only trick here will be keeping the flyback secondary far enough away to not couple to the probe much. A simple grounded shield, such as a grounded piece of sheet-metal or foil, propped roughly at the flyback transformer is likely enough to separate primary and secondary electrostatic fields.
Post by: SteveN87 on April 16, 2020, 08:25:32 PM