GDT Slow Rise/Fall times even with resistor shorted

[SalinsLV]

Hello!

While building my first DRSSTC i've ran into an issue. The rise/fall times at the mosfet gate are too slow at ~450KHz frequency. Here's an example:

Probe connected at the gate of the mosfet:



When i short the gate resistor i get a 2x faster rise and fall times but they are still too slow:


The waveform at the drivers output looks like this:


This is how my entire setup looks like:


Driver+interrupter:


FULL-bridge:


FULL-bridge schematic:


FULL-bridge layout which is approximate and used only for reference:


GDT (1:1 ratio for all windings. 1 center, 4 gate windings):



I have tried the following:
*Removed 18V regulator that wasted 1W of power while doing nothing (Gate Waveform still the same)
*Increased power supply current to allow 2A max for the driver (nothing changed)
*twisted wires to reduce interference, cut all long wires to shorter length and removed those high resistance alligator clip wires (waveform had less interference but rise/fall time still the same)
*Added 2200uF capacitor at the power input (Drastically improved waveform balance- it was stuttering and jumping around without bus cap but rise/fall time still the same)
*Connected GDT directly to mosfet gate (as previously mentioned, this made the rise/fall times about 2x faster ~500ns -> ~270ns but they are still too slow)
*Removed All mosfets and got this waveform at the gate terminal:

However, when the mosfets are placed back into the terminals the waveform goes back to the same as in the first picture:



I think that this isn't the drivers fault as the rise/fall times at the drivers output are ~44ns (Even when the GDT is connected to the driver and loaded with mosfets). The problem should be somewhere in the GDT itself or the FULL-bridge design, however with the attempts i mentioned above i haven't been able to get the rise/fall times faster than ~270ns at the mosfet gates.

[davekni]

With gate resistors bypassed, your gate waveforms look great.  DRSSTC H-bridges should switch close to zero current.  Vgs rise/fall times do not need to be particularly fast when switching low currents.  Also, these FETs are specified for 10Vge operation.  The relevant switching time is 0Vgs to 10Vgs, and from 10Vgs to 0Vgs (or slightly more to account for FET internal gate resistance, which doesn't appear to be specified for IRFP360).

If you want to further decrease rise/fall times, GDT leakage inductance needs further reduction.  One simple change is to reduce GDT turns.  Presuming a reasonable ferrite core (not powdered iron), 2 or 3 turns is likely plenty for 470kHz.  (Looks like your core has at least 50mm^2 cross-sectional area.)  Fewer turns shortens total GDT wire length.  Leakage inductance is proportional to wire length, including leads.  (Nice job with GDT winding and lead twisting.)  Another GDT change could further reduce leakage inductance:  Change from one primary wire to 4, one twisted pair winding for each FET, with all four primaries paralleled.  See this post for construction details:
https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949

Are you planning to run your H-bridge at 35V or less?  Looks like a 35V bypass capacitor at the bridge.  If you do plan higher voltage (and a cap change) eventually, you may want to consider lower parasitic inductance in bridge construction too.  This example starts with a half-bridge, later updated to full bridge.  Details aren't critical, just the idea of overlapping parallel planes:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

Great post too.  Plenty of detailed pictures and scope captures.

[SalinsLV]

(Nice job with GDT winding and lead twisting.) 

Thanks!

Are you planning to run your H-bridge at 35V or less?  Looks like a 35V bypass capacitor at the bridge.  If you do plan higher voltage (and a cap change) eventually, you may want to consider lower parasitic inductance in bridge construction too.  This example starts with a half-bridge, later updated to full bridge.

My plan was to make the driver and GDT waveforms as good as possible before I even attempt to build something more powerful. That's why I built a simple H-bridge with mosfets that i don't mind destroying. I've had bad experience by using expensive IGBTs with a driver that gave horrible waveforms, causing over +20 IGBT and mosfet deaths. I will definitely use rectified mains later on, but now I should master the basics. The current H-bridge with IRFP360 is a test bridge as I wanted to make the waveforms clean before using higher power IGBTs.

  Fewer turns shortens total GDT wire length.  Leakage inductance is proportional to wire length, including leads.

I really did not want to cut the current GDT wires shorter but I will create a similar GDT with shorter wires, in the upcoming days. However I did notice that the waveform improved when i lowered frequency:
Yellow - Driver output
Blue - Mosfet gate terminal
~418Khz


~176KHz


~120KHz


~41KHz


Should I ditch the idea of using smaller 470KHz coil and instead replace it with ~200KHz coil?

[davekni]

As far as the transition, does the step function create a rich brew of frequencies, one of which is close enough to the secondary frequency to start the oscillation?

If you already have a 470kHz coil made, no reason to change.  Your gate waveforms are fine, as I said in my last post.   Just run at reasonably low interrupter duty cycle initially to make sure your driver chip and gate resistors don't overheat.
On the other hand, 200kHz is easier in several respects, especially once H-bridge voltage is higher.  Switching losses are lower in the FETs (or IGBTs), gate driver and gate resistor power is lower, and driver phase lead adjustment is easier.  (At 470kHz, delay through the comparitor, gate driver, and IGBTs can approach 1/4 cycle, 90 degrees.  That is more than typical UD2.7 or similar phase lead can undo.)