First middle sized DRSSTC - Phase lead tuning

[Rapy2]

Hi, I'm just building my first middle sized DRSSTC. I mentioned this in my last post. I am attaching some pictures of my setup. I use double bridge made of 8 HGTG30n60a4d with davekni´s bridge design, driver UD2.7C. Its oscilating at around 120 kHz. Yesterday I tried first static load test and tried to set the phase lead. I run the bridge at around 190V from my variac, 400A OCD, it looks great, first 3 cycles have some spikes, but then there are 8 cycles with almost no spikes, so this should be fine, the cycles with the highest current are clean. Unfortunately, it is impossible to set it so that all cycles are without spikes. But then if I increase the bridge voltage just by 20V to 210V, the current suddenly rise faster and with the same OCD limit, there are just 8 cycles and 4 of them have spikes. I don´t like it. I am not sure if this is ok, because I want to run the bridge finally at 325V bus voltage at around 600A peak. I think that it will be impossible to run the bridge at this voltage, because with my setup of this primary coil and 100n capacitor bank the current rise very fast and there will be probably just 2-3 cycles to get 600A of current. I don´t want to change my primary, because it took lot of time to make it. Would it be better to reduce the capacity and add turns on the primary or increase the capacity and remove some turns? Thank you for any advice. Tom

[davekni]

My guess is that the dead-time isn't sufficient (one IGBT pair isn't off before opposite pair starts conducting).  That would explain why it is difficult to eliminate spikes with phase lead adjustment, and why spikes get worse at higher bus voltage.  My example-layout H-Bridge with 8 TO247 parts uses 50 ohms/IGBT.  Your IGBTs have about twice the gate capacitance, so ~25 ohms/IGBT may be about right (somewhere around 20-30 ohms).  It looks like 10 ohm resistors in your images, probably not quite enough for sufficient dead-time.

If you try increasing gate resistance as I'm suggesting, phase lead will need to be increased some to match the increased turn-on delay.

Layout looks clean.  I see no issues there.

[Rapy2]

Hi davekni,
thanks for your advice. You are right, I use 10 ohms gate resistor/IGBT, each IGBT has its own resistor and they are conected in the middle with another one from the pair. The problem is probably caused by the gate resistance, because I don´t really know how to find the proper gate resistance. I just tried 10 ohms. I will try to add 10 ohms resistor to the middle connection.

[davekni]

I'm not quite clear on what you are about to try.  Are you adding one additional 10-ohm resistor for each pair of IGBTs?  If so, two things to consider:
1) That new 10-ohm resistor needs a diode across it to keep turn-off fast.
2) That single 10-ohm resistor is the same as adding 20 ohms to each gate, for 30 ohms total per gate.  That may be fine.  Vge rise time will be 3 times longer.

[Rapy2]

I already tried to add one 10 ohms resistor common for both IGBTs in pair. If am correct it should be 20 ohms per IGBT, if I measure resistance between wire from GDT and one Gate it is 20 ohms . But it didn´t help, and if i look to the gate signal, it has too slow rising edge, so it looks like the gate resistance is too high, I am going to try replace that new 10 ohms resistor with 4,7 ohms. About the diode, you are right, I forgot to place the diode across the resistor, I will add it.

EDIT: My gate waveform looks now like this. Before adding the aditional resistor it has some spikes.

[davekni]

Yes, if you measure resistance from GDT to a single gate, you read 20 ohms.  However, the GDT is driving both gates simultaneously.  Instead consider the resistance from GDT to both gates together.  That will measure 15 ohms (two gates shorted together, measured to GDT lead).  Before adding the extra 10-ohm resistor, GDT to the two gates together would measure 5 ohms.  It is now 3x higher (15 vs 5).  Vge rise time will be the same as with 30-ohm resistors for each gate.  (30 ohms on each gate would also measure 15 ohms to the two gates together.)

Some negative spiking is expected on Vge waveforms.  That is expected as a result of GDT leakage inductance and gate capacitance.  Some people add small resistors in series with the diodes to minimize this negative spike.  (My diode series resistors are 1/5th of the main series-resistor value.)

The rising Vge waveform needs to be rounded (slow) in order to provide dead-time.  Some integrated driver chips provide dead-time without slowing edges.  The simple diode/resistor network used by most hobbiests has the artifact of slowing (rounding) rising edges.  (The rounding can be reduced a little by adding tiny inductors in series with the series resistors, making Vge rising edge critically-damped rather than underdamped.)

BTW, I presume your gate diodes are fast-recovery or schottky.  Standard slow diodes such as 1N4004 could cause insufficient dead-time.

[Rapy2]

Thanks for the explanation. Every time I think I understand, I'm misled  I didn't realize that I was increasing the gate resistance 3 times.

In some designs, I have seen that they use a small resistor in series with the diode.

Although my Vge waveform is currently rounded and it should provide some dead-time, it looks like it does not make any change at my Vce waveform. There are still some spikes in the first 3 cycles. I tried to set the phase lead again. Now I will try to replace the additional 10 ohm resistor with a 4.7 ohm resistor, see if it will make any changes.

My gate diodes are schottky 1N5819.

[Rapy2]

Well, adding 4,7 ohms resistor makes it even worse, now I am unable to set it clean at all. Adding 10 ohms resistor makes almost no change, maybe it was little bit worse and with 4,7 its completely bad.

So far I get the best results with the original design (10 ohms resistor for each gate). Maybe my layout is not good enough to completely remove spikes. My snubber caps are 4x MKP10 4,7 uF, this should be fine.

[davekni]

There are usually some Vce spikes at low current.  Even with phase-lead, there is not enough remaining current in the primary to cause the Vce voltage transition within the dead time.  If you have spikes at high current and high voltage, that is the problem to avoid.

Extra phase-lead is usually better than too little.  Extra phase lead may make some lower-voltage wider spikes, usually not large enough to cause trouble.  If dead-time is sufficient, you should be able to see some tripple-transitions on Vce (single cycle ring during transition) when phase-lead is slightly too low and current is high.  If you cannot find those with phase-lead adjustment, then I'd suggest staying with your added 10ohms (30 ohms/gate) rather than dropping to 4.7 ohms for the added resistor.  (Just read your latest post.  Zoom in to the edges to see.  Perhaps "not clean" is the tripple-transitions.  If so, add a bit more phase-lead.)

Here's another explanation of why adding 10 ohms results in 30 ohms per gate, in case this makes more sense:  Consider making each gate resistor 30 ohms by adding 20 ohms in series with each initial 10-ohm gate resistor.  That is explicitly 30 ohms/gate, as each gate has it's own 10-ohm resistor and it's own 20-ohm resistor in series, making 30 ohms.  Now connect the center of the 10-20 ohm resistor sets between the two IGBTs.  Now the two 20-ohm resistors are in parallel, making a single added 10-ohm resistor.

[Rapy2]

In my original design with 10 ohms resistor for each gate there were some spikes, but just at the start where the current is not higher than 30% of the peak current. Last few cycles were perfectly clean.

At this point, I need to experiment with different gate resistor values and see when it works best.

As I wrote in the first post, I'm afraid that when I increase the voltage on the bridge, the current will reach around 500-600 A in just a few cycles and then the Vce will have peaks still at about 50% of the maximum current instead of 30% as I have it right now with lower bus voltage.

Thanks for explanation, now its compleately clear to me.

[Rapy2]

Just tried to set the phase lead best I can and go up with the voltage. I also increased the OCD to 500A. I am attaching Vce wave and zoomed first cycle. That is at full expected voltage 325V bus and 500A limit. I think maybe it won't be a problem to run it like this. First cycle has the biggest spike, but the spike is just 40V. I plan to run it at 600A later.

[davekni]

Noticed one thing that would help reduce inductance in VBus:  For the 4.7uF film capacitors, instead of soldering the ends of the leads, bend the capacitor leads out horizontally.  Bend the leads out sharply where they exit the capacitors.  Then the capacitors will sit almost-flat against the circuit board, reducing lead inductance.  That is the way I built my example H-Bridge (and every other project where leads solder to the component-side of a board).  This is not a critical change.  You already have lower VBus inductance than most builds.  Just a thought in case you are reworking things some day.

Yes, those traces look great.

[Rapy2]

That's a good idea, thanks. If I know that something can be improved and I know how, I always try to do it. I will rebuild it tomorrow.

And thank you again for your help. I really appreciate that.

[thedoc298]

Really enjoyed following this thread. Nice to learn from the experts on this forum.  Rapy2, your work looks very very good and I believe it will give back to you. I am about the same place in my development and this helped out much.


Thanks

[Rapy2]

Thanks, I am glad that it helped. Good luck with your build!

[Rapy2]

Just information for other DRSSTC builders. These transistors look very promising in DRSSTC use. I have double bridge made of 8 pices HGTG30N60A4D transistors. So far I tested it with rectified mains voltage 325Vbus and OCD set to 600 A, running at 125 kHz, in my scope I can see it usually rises up to 650 A before it crosses zero and shuts down. So far, I haven't tried to increase the peak current yet. The transistors run nicely, they don't even warm up. I am currently limited by the size of MMC, I use FKP1 1250V 100n 4 in series and 4 in parallel for a total of 100n. This MMC is not enough, the capacitors become very hot after only a minute.