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Messages - Power-Max
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1
« on: July 26, 2021, 03:29:32 AM »
just add a zener, it hasn't too many capacitance to mess something up. my design uses two 12v zeners back-to-back. not a supressor, it has a big capacity. also, with 600v d-s you will be able to supply it 70v max, my irfp260 drain sees 350v on it at just 35v, i still don't know why it doesn't burn. anyway, it should be good enough. zeners must be as close to gate and source as possible. also, about design improvements, make the gate voltage divider work from separate 12v source, that way you can interrupt it, ramp it and make a lot of nice stuff. the tuning will be much easier with some scope. good luck:D
Yeah I keep frying the FETs.  I have to walk a very thin line with the ratio of the capacitors to prevent exceeding the Vgs rating of the MOSFET. I thought about adding a zener diode but the capacitor divider with the high reactive currents form a very low impedance drive and clamping the voltage would seemingly result in blowing the zener diode. If there was a way to dynamically adjust the capacitor divider ratio as the oscillation grows to full magnitude that'd be ideal! I came up with some pretty convoluted ideas in LTspice but at these frequencies propagation delay is a serious concern that has a massive impact on performance.
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« on: June 27, 2021, 07:05:16 PM »
Circuit breakers are intended to protect the wiring in your walls, nothing else. Unfortunately this does not apply to extension cables and such things external to the walls, or any loads. This means it is possible to power a high load appliance (microwave, kettle, etc) on an extension cable that isn't rated for that use. Worse if the cable is long and coiled up, and cheap 18AWG crap, and even worse than that, some extension cables use PVC insulation and PVC jacketing, which can get soft and melty at relatively low temps and releases lots of very toxic fumes when it burns.
3
« on: June 27, 2021, 06:54:41 PM »
Yes, ZCS operation is difficult to obtain in SSTCs. That is why most are designed with FETs instead of IGBTs, and without attempting to hit zero-current switching. Also, yes, primary current feedback tends to lock to the lower pole frequency. QCW coils usually operate at the upper pole frequency, requiring extra circuitry to force operation there.
Do you have diodes across the 6.2 ohm gate resistors? That is necessary to avoid the miller-capacitance issues you are seeing. If you already have diodes, then your driver chip is not strong enough for the IGBTs being used, or you need larger gate resistance value to slow turn-on speed.
I designed the board with the intent of using HY1920W or HY1920P MOSFETs (same part but one is a TO-220 for $0.70 ea, (more like $1.40 now with the silicon shortage, the TO-247 one is $1.40 on average) and it popped at least one of them instantly. Also, strangely, the 15nf||6.2ohm snubber keeps burning up with the MOSFETs but not with the IGBTs, the output waveform is much more square with MOSFETs. My calculations predict 1W of power dissipation RMS, but maybe the peak power is killing it. Also it is only the one side connecting output to VCC, not output to GND. Very strange! I am using this arrangement of NPN and PNP diodes to drive the IGBTs. I breadboard tested it with 15nf capacitor emulating the gate charge, and it seemed to work fine. I can solder a diode on top of those resistors. (those resistors are massive and they get hot! As does the current amplifier) If I redesign this board, I'll probably use a local current amplifier near each IGBT rather than doing this single driver driving 2 paralell IGBTs. and probably not the 2222 series BJT's, they seem to be rather slow. Or probably just fix all the problems by going with a GDT like everyone else lol
4
« on: June 27, 2021, 08:47:55 AM »
I got a whole bunch of FCA35N60 MOSFETs, rated 600Vds and 90mOhms. Although the capacitance are a bit high on it. I was thinking about making one of those fancy HFSSTCs with it. I wound a secondary and it clocks in at around 7-8 MHz when energized from a function generator. The circuit I'm using is the very simple one with the DC bias voltage applied to the gate, a small capacitor on the gate connected to ground, with a series LC primary connected drain to gate. The big problem with this type of circuit seems to be the the unregulated feedback. MOSFET gates are notoriously picky about voltages, and I have to tread carefully so as not to overdrive the gate or exceed 24Vpeak-peak or thereabouts. I thought about redesigning the circuit to operate as common gate, so that the input impedance is very low and the energy gets recycled into the oscillator, but the problem is it's stable (I think common base amplifier is not inverting and hence stable) I need to find a way to invert the phase. But anyways, regarding the normal circuit, should the ratio of the additional gate-source capacitance and the series LC capacitance be conserved? I most versions of the schematic I came across appear to use 100pF for the tank capacitor and ~4nF for the gate-source shunt. Can these values be scaled proportionally to increase or decrease the operation frequency? I already killed a few of my FETs messing about lol
5
« on: June 24, 2021, 08:23:55 PM »
Oh something I did actually think about: On the CD4046, you have the VCO output, and you have the comparator in feedback pin. Pins 4 and 3 respectively. If you connect the output of the H bridge (through a voltage reduction network and some filtering) to pin 3, it should theoretically be possible to have the PLL make up for any propagation delay in the rest of the driver circuit stuff. In practice I found due to ground loop issues the PLL had a hell of a lot of phase noise and wasn't locking all that good. I might add an SR latch to the output of the DTI circuit. Set when the top IGBT is commanded ON, and Reset when the bottom IGBT is commanded ON. This does not include the IRS2186(S) in the feedback loop so that propagation delay and that of the IGBTs will go unchecked, unfortunately. But at least I can account for the significant delay caused by the DTI. And also add some delay elements as a form of feedforward compensation. Or on the analog VCO side, make up for it with the current source and sink connected to the VCO INPUT, introducing a constant current to tug up on the voltage and keep the CD4046 locked but VCO OUTPUT phase slightly leading by the same amount. Phase Locked Loops are now my most favorite electronic component haha! I need to study up more on closed loop control, stability, root locus and poles/zeros transfer functions and so on. 
6
« on: June 24, 2021, 08:13:36 PM »
I developed this experimental PLL driver circuit. I am using a bootstrap driver rather than a GDT. (I might have to redesign the board to use a GDT, though. As with my 60N60 IGBTs, I can't keep the gate pulled low).
I noticed that the H bridge output tends to have quite a high propagation delay from the input to the IRS2186 (which itself has 170ns delay, plus the delay of the IGBTs). The dead-time insertion circuit is implemented with a quad XOR gate, the 74HC86. The schematic shows a more complicated version then what I ended up using in the end (no BJT was necessary following the first XOR gates, current sources replaced by 1K resistor, approximately 300ns of dead time, probably a bit much, the resonant frequency is about 220kHz to 320kHz)
The dead time is probably a bit high. How little dead time can I get away with? What I understand is that IGBTs have a reverse recovery period like diodes, there is a certain amount of minority charge carriers or something that must be depleted. So if no dead-time is implemented, there will be a few hundred nanoseconds or so where both IGBTs are conducting, long enough for this minority charge carriers in the IGBT that is supposed to be off, to deplete. If that's the case the average switching loss from this reverse recovery time will be F*Q*V where F is frequency, Q is how much charge is stored in the IGBT, and V is voltage. I think it works out to a around tens watts or so. Peak power is a different beast, and I might be putting an unnecessary strain on the IGBTs at the edge of the SOA, though. Peak currents from this shoot-though would result in EMI but for a tesla coil it is a minor source of EMI lol.
How much dead-time should I program in? I might half it and set it to the datasheet's specified reverse recovery time. So at least most remaining charge in the IGBT can be dumped into the primary rather than wasted as heat in the IGBTs, and to hopefully prevent issue with multiple self-actuations of the voltage on the primary which can result in hard switching.
Also if you smart guys have any input on my half bridge layout and circuit I'd love to hear it! It is rather annoying to have so much propagation delay and no galvanic isolation between driver and half bridge with this current design. This is a design I want to be able to sell after making a tutorial video on building a TC. Adding optocouplers increases cost and further worsens propagation delay. I could add even more delay deliberately to get it to 180 degrees closed loop, then flip the phasing of the feedback or primary to get 360 degrees, but I kind of prefer 0 degrees phase lead rather than 360 or 320. Is that achievable?
If hard switching is allowed, is it possible to audio modulate by either modulating the dead time (that was the original idea with the variable dead-time circuit, controlling the current sources on the quad XOR gate circuit to actively modulate the dead time and also propagation delay. Ended up not working particularly well, though)
7
« on: June 24, 2021, 05:31:20 PM »
I thought the SSTC is supposed to operate in the ZVS condition when tuned properly?
DRSSTCs almost always run in ZCS mode (close to zero-current at the bridge switching point). SSTCs can run ZCS if coupling and secondary Q are high enough. Many don't run ZCS. Using feedback from the secondary (antenna or coil current) makes ZCS difficult to achieve. ZCS refers to switching close to zero primary current. DRSSTCs use primary current feedback, making ZCS easier to achieve.
I tried to run the half bridge SSTC with primary feedback in LTspice, but found it almost always ends up running the DC blocking capacitors like resonant capacitors, resonating in the low kHz range, or some parasitic oscillation in the low MHz range, depending on the propagation delay and phasing. This makes sense looking at the phase of the current compared to the excitation voltage. The phase is not that well behaved and not monotonic. The simulation assumes no DC blocking since it is an AC simulation anyway. I could add a series capacitor to see what ends up being the third peak below the anti-resonance and resonance peak of the SSTC. But for now, I found a potentially serious issue. Besides the fact my bootstrap half bridge w/ dead-time insertion circuit has something like 700ns of total propagation delay, leading to an almost 90 degree phase lag, I used 6.2 ohm gate resistors and BJT totem pole arrangement of common emitters following the IRS2186 IC, I observe massive miller effect when the low side IGBTs is turning on. The gate on the low side IGBT gets pulled up to about 10V when the 110V HVDC supply is applied. Output of half bridge left open circuit. Gate drive is clean with no HVDC supply, following a pretty decent following a pretty decent RC characteristic. Placing an additional 1nf capacitor directly across the gate and emitter of the IGBT has almost no effect. high frequency crap is observed on the output of the BJT. (I am using PN2222 and PN2907, perhaps the bandwidth of these devices just isn't high enough) I'm thinking that a board redesign may be necessary to place those current amplifier BJTs much closer to the IGBT. or perhaps remove them and use 2 IRS2186 IC's to drive both pairs of IGBTs, this gives the freedom to have them run in either half bridge (2 paralell top and bottom) or full bridge (running out of phase)
8
« on: June 24, 2021, 04:06:40 AM »
My guess for non-50% duty cycle is the phase comparitor output filter bandwidth is too high. That allows significant VCO-frequency signal to get through to the VCO input.
Most people use FETs for SSTC. With feedback from secondary (antenna or secondary current), it is difficult to get bridge switching just before primary current zero-crossing. IGBTs have too high switching loss at 100+kHz to use with hard-switching (switching away from current zero-crossing).
Thank you for this input. I thought the SSTC is supposed to operate in the ZVS condition when tuned properly? I opened up LTspice to perform a quick AC simulation (250kHz to 300kHz) to see what's up. I set L1=5uH, L2=25mH (3.5in dia., 10", 950t), Cs=14pf, R1={100k -- 5000Mega} (.step param secondary load), R2=10mOhm (primary series resistance to prevent issue of voltage source across inductor). I found that secondary current feedback can be used to lock on to the secondary frequency, as it is very well behaved, with phase lead < resonance and phase lag following resonance. The median point is where maximum voltage output is achieved. And also as long as the Q factor is high enough and/or the coupling is tight enough, it seems that the phase crosses zero. I don't know if in reality it will be possible to achieve this condition. The phase of the primary current relative to the excitation voltage is rather strange. It crosses over from inductive region (90 degrees lagging) up into the capacitive region (up to leading as much as 90 degrees), then at the resonant frequency dropping back down into the inductive region. If the coupling is weak or the secondary Q factor is too low (the resistor R1) the result is the phase goes up and down much more gradually, and may not reach fully into the capacitive region. If this is the case, then at the resonance the primary current will be lagging significantly.
9
« on: June 23, 2021, 06:56:19 PM »
Yes, too little or too much load will lead to large primary currents. This equation describes it:
Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec)
Qpri is the effective Q of the primary tank due to its power loss to the secondary, k is the coupling, f the frequency the coil is running at, fsec is the secondary resonance frequency and Qsec the Q of the secondary caused by the arc load. A low Qpri implies an effective energy transfer to the secondary.
The equation is the sum of 2 terms, one having Qsec in the numerator and one in the denominator, so either Qsec being too large (=little arc load) or too small (=too much arc load) will cause a large Qpri, i.e. a large primary current. A large coupling k also reduces Qpri. The same is true for good tuning, i.e. f near to fsec, which makes the first term small.
This is super enlightening, and seems to translate to my superficial observations! How was this equation derived, using the transformer model? The hard part would probably coming up with accurate figures for secondary Q factor and since the arc acts as a highly nonlinear load which is approximated to a variable shunt RC circuit. So we know a high Qpri is bad. High Qpri conduction occurs when either term approaches infinity. The second term, (K 2*Q sec) -1, grows large when the denominator approaches zero, when either the coupling approaches zero (running w/o a secondary) or when the Q factor of the secondary is very high itself (when it is short-circuited for instance, rejecting all magnetic flux) or if the topload does not permit breakout and acts as a high Q capacitor to the environment only. The first term also approaches infinity when coupling approaches zero or Qsec gets too large, or if the term (1-f^2/fsec^2)^2 gets too high, which occurs at very high f. This last one is the least intuitive and is the most confusing. At high frequency, the inductive reactance dominates, the current will be triangular due to Xl dominating, and the current would be limited by Xl. This term f confuses me even more because, from what I've observed, when 2 coils are coupled together the primary and the secondary resonant frequency both are impacted and change. As I understand from the transformer model, the impedance looking into the primary, you end up seeing both a magnetizing and leakage inductance, and the secondary RLC network is reflected to the primary via the turns ratio squared. (my knowledge on that model is a bit rusty though, but end result is a rather complex RLC network with multiple poles and zeros and LTspice plotting the voltage gain shows 2 resonant peaks and something I'll call an anti-resonance between them. The 2 resonant peaks tend to come together as K is reduced and spread apart as K is increased. Which of these resonant peaks is preferred? I suppose the lower peak is more the result of the magnetizing inductance and the higher one more the result of the leakage inductance? Is is possible to construct the TC driver such it stays locked to only one of these peaks, is one of them more stable with arc loading? Is having the primary and secondary resonant frequency independently tuned to match ideal? (suppose secondary with large breakout runs 270kHz, tune the unloaded primary to also run at 270kHz?) In the interest of saving my IGBTs (I bought a whole bunch of cheap 60N60 devices from LCSC, and HY1920W FETs to try out), is it worthwhile to use linear primary current feedback (resistor instead of back-to-back diodes) and set an inhibit pulse of fixed length (on the order of hundred milliseconds to a few seconds) using a LM339 comparator? Idea here is that when primary current exceeds a set limit, when the limit is exceeded the signal driving the gate drive IC is suppressed so the H bridge is disabled. Maybe through a flipflop with the RF feedback fed into the clock so that it disables and enables on a zero crossing. Not sure if that's really necessary though
10
« on: June 11, 2021, 06:32:02 AM »
For feedback, your options are:
1) Add enough phase-lead to compensate for the delay.
2) Invert the feedback and add enough phase-lag (additional delay) to get almost another 180 degrees of lag. I say "almost" because half-bridge switching is most efficient and clean when voltage changes slightly before current zero-crossing.
For your situation, I recommend (2) above. Adding delay is easier, especially given how much delay you already have. I've used three stages of series resistor and parallel (to ground) capacitor for this purpose. Each stage is progressively higher impedance (higher R, lower C) to minimize load on previous stage.
For PLL operation, design the PLL to have a narrow frequency range and fixed 50% duty cycle. That way it cannot lock to harmonics.
One variation on a narrow-band PLL that I've used: Start with an open-loop L/C oscillator feeding the bridge. Adjust it's frequency (variable inductor in my case) to your desired center frequency. Then add a turn around the inductor as loosely-coupled magnetic feedback. In my case (SSTC), this turn was secondary current.
I set my PLL to run at between 180kHz to 320kHz (this range may be a bit on the high side) with a 100pF capacitor and I forgot the values of R1 and R2. I am using the digital memory network, as I want to reduce the phase lag, instead incorporate phase lead. I do this by then adding a BJT as a current source to the VCO capacitor to inject a constant current into the capacitor, creating a permanent offset and a phase lead. The output of phase comparator II is then constantly trying to compensate and switching early. If I go too far the coil output diminishes significantly and gives very hot and short arcs. I notice that under certain conditions the output from the PLL has a duty cycle that can be quite off from 50%. What causes this? IGBTs also tent to get quite toasty. I need to see if it's ohmic or switching losses, I just wired up a current transformer today but one of the IBGTs gave up before I got a good reading of the RMS voltage of the 0.1 ohm resistor. The current waveform was very distorted and seemed to have an amplitude around 200mV or so. With a 30:1 winding ratio that seems to be about 60A? Running with 2 turns and 110V ~8A input, continuous duty. I guess that is about 240W of power dissipation... Using a CPU heatsink with a 80mm PC fan running on the 15V supply
11
« on: June 10, 2021, 05:10:24 AM »
I built a half bridge using some IGBTs, 6 ohm gate resistors, a 2222 and 2907 totem pole current amplifier, the IRS2186 bootstrap gate driver IC, which is driven from a Dead-time-insertion circuit that delays a rising edge by about 200ns and the falling edge by the smallest amount possible, by about 50ns or so).
The problem is when I attempt to close the loop using antenna or secondary base feedback (into anti-parallel high-speed diodes) the output isn't what I expect. The circuit is a good bit away from resonance. And I suspect it may have to do with all these propagation delays adding up: 20ns or so for the IGBTs (turn-on delay), the 170ns of the IRS2186, and the 200ns of dead-time insertion from the circuit I made using some RC circuit, diode, and 74HC86. It all adds up to a maximum worst-case of about 600nS. Or about 20% of the operating frequency (assumed 300kHz, it is actually 320kHz small-signal and drops to 270kHz when approaching the secondary with a ground rod or ground plane or with decent breakout).
If I drive the input with a fixed frequency from a function generator and manually tune it, I can get nice 1 foot long hot continuous wave arcs, and I'm pumping about 880W (measured about 8A) from a 110VDC power supply. I also tried making the circuit have variable dead-time to adjust the power going into the arc but unless I allow it to have an open streamer to air (maximum loading, and maximum damping of secondary) this is not a good technique for audio modulation. I need to be able to pull power back out of the resonant network and return it to the supply, which is done by running out of resonance.
I suspect this may be one of the reasons I can't quite get my PLL tesla coil to work right once I close the loop. I occasionally fry these stupid gate driver ICs or my IGBTs when my PLL locks onto some weird harmonic or outputs a non-symmetrical square wave causing issues for the half bridge
12
« on: June 10, 2021, 04:50:34 AM »
Does it really matter, considering thermal transfer package to heatsink is limited , especially if you use some form of insulation and not just grease the surfaces?Even the attachment of the capsule has significance. Making the heatsink slightly larger so that the sum of thermal resistance stays the same is easy.
Especially some manufacturers states ridicuosly high power capabilites based on theoretical calculations. I mean, 350W in a TO-220? Seriously?
This dissipation rating or Rth j-c is mostly indicative of how large the actual semiconductor is, so one with half the Rth (or 2X the Pdiss) is indeed about twice the area and consequently will have more volume to absorb the high power losses in pulsed applications. The dissipation rating is obtained by assuming 25*C tab/interface temperature with Tjmax (150 or 175*C typically) applied to the junction and measuring the power flow from the chip, so its not a "practical use" rating, but still a reasonable metric to compare by.
So even though the Rth of the device itself is only a small portion of the total thermal resistance stackup (typical TO-247 insulator might be ~1*C/W) the fact that its a bigger chip inside means it has lower transient thermal impedance and will handle greater pulse power. Even for non-pulse power designs, it can really help to pick the biggest chip size for a given package to increase the power density of a design, and some designs really can appreciate the .2 to .5 *C/W reduction of going from a wimpy device to a strong one.
' I agree 100%. I have also found from experience that some PMOS transistors I have, tend to tolerate a bit more abuse than equally current-rated NMOS devices, I expect it's because NMOS has approx. 3 times better electron mobility which means the die size is physically smaller for the same current handling. Smaller die also means smaller parasitic capacitance. This is especailly true for GaN or SiC devices. If you pick one with the same current rating as the silicon one, the die will be smaller and not be as tolerant to abuse. The capacitance and gate charge figures are also reasonable metrics to go by when trying to judge die size. It would be nice if manufactures just straight up specified the thermal impedance rather than steady-state thermal resistance. I suppose they sort-of do in a roundabout way via the Safe Operating Area graph.
13
« on: June 09, 2021, 08:02:15 PM »
My very rudimentary understanding is that if perfectly in resonance (there are 2 resonant peaks with a DRSSTC and one anti-resonant peak which is quite annoying) they shift around with arc loading and how "deep" they go depends on the arc loading, as this can be modeled as a RC network as a secondary load. I need to figure out how to model a loosely coupled transformer like this better. The transformer model and reflecting impedance across a behavioral voltage/current source (used in the transformer model). I did this back in college with transformers and transistor models but I'm rusty lol)
But if I understand it right, what might be happening is with a worst-case load on the output (either no breakout at all or a dead short circuit on the secondary) what is happening is that the Q of the transformer network is only limited by the Q factor of the series resonant capacitor network and the effective resistance of the primary coil. MOSFETs or IGBTs are nearly always the limiting factor as their effective ohmic losses is about an order of magnitude or more higher that good quality tank circuit.
14
« on: June 03, 2021, 04:52:20 AM »
I added an extra diode(1n4004) between source-drain to reduce load on the internal diode. I also added a gate-source resistor and soldered the circuit together with a fairly big heatsink attached (I initially breadboarded it  :P) to reduce the stray inductance , but the fet is still finger-burning hot after a 2 min run.
1N4004 is a slow diode meant for mains rectification. Take a look at the specs, specifically junction capacitance and especially reverse recovery time. You want a diode that has a reverse recovery time measured in nanoseconds. The UF4007 comes to mind. small signal diodes (like 1n4148) come to mind for low currents and medium voltages, and schottky diodes come to mind for high currents and low to medium voltages.
15
« on: June 03, 2021, 04:32:53 AM »
I almost managed it. /> I am using HY1920P MOSFETs (90A, 20mOhms, 200V) powered with rectified mains (video suggests 110VDC from 2 supplies, but most of the shots were with direct 170V mains) Problem is under certain arc loads the secondary pretty much rejects the magnetic flux and this seems to cause the reactive energy in the primary to build up to levels high enough to blow my MOSFETs. I've since beefed up the H bridge by doubling down on the MOSFETs and using Class 1 ceramic capacitors in place of MKP film capacitors for the much lower dissipation factor and higher Q factor. This improved the performance considerably but results in blown capacitor! I'm not too surprised, using just 8 15nf 1210 size capacitors. Damn impressed they could handle it anyway. (I think I figured out the AC voltage was getting on the order of 1KV on the primary based on the calculated reactance) The thing I don't understand about DRSSTC's is what the impedance looks like looking into the primary. In Spice, I can see that even if you take a primary and secondary tank tuned to the same frequency and then couple them together, you always end up with 2 resonant peaks, dependent on the coupling coefficient. the less coupled the closer the peaks.
16
« on: June 03, 2021, 01:33:54 AM »
The thermal resistance is 0.53 K/W which is pretty bad IMHO. I got some ON semi 60N65 parts with a thermal resistance of 0.25 K/W. I've also seen TO-220 package devices with lower thermal resistances. This matters when you are dissipating a good deal of power due to hard switching or high RMS currents.
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[Spark Gap Tesla Coils (SGTC)]
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NyaaX_X
April 18, 2024, 04:03:38 PM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 18, 2024, 02:56:40 PM
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Re: DIY induction guns? (warning:long)
[Induction Launchers, Coil Guns and Rails guns]
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Benbmw
April 18, 2024, 06:17:15 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 18, 2024, 05:46:07 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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MRMILSTAR
April 18, 2024, 05:18:31 AM
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Re: IKY150N65EH7, is it good for DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 18, 2024, 04:34:52 AM
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Re: How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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klugesmith
April 18, 2024, 04:11:53 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 18, 2024, 04:02:44 AM
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Re: 100kHz CM300 gate resistor choice
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 18, 2024, 03:35:52 AM
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Re: How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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MRMILSTAR
April 17, 2024, 11:54:05 PM
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100kHz CM300 gate resistor choice
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Benjamin Lockhart
April 17, 2024, 11:37:16 PM
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Re: Has anyone tried to build a TMT (extra coil) Tesla coil?
[General Chat]
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Michelle_
April 17, 2024, 02:29:30 AM
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Re: Has anyone tried to build a TMT (extra coil) Tesla coil?
[General Chat]
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MRMILSTAR
April 16, 2024, 11:56:12 PM
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Re: How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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klugesmith
April 16, 2024, 11:46:57 PM
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Re: How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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Bobakman
April 16, 2024, 10:40:11 PM
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Has anyone tried to build a TMT (extra coil) Tesla coil?
[General Chat]
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Michelle_
April 16, 2024, 09:21:39 PM
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Re: Medium Drsstc question
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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flyingperson23
April 16, 2024, 08:04:16 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Benjamin Lockhart
April 16, 2024, 06:48:05 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 16, 2024, 06:18:40 PM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 16, 2024, 06:14:53 PM
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Re: 3D printed mini-slayer: world's weakest tesla coil
[Solid State Tesla Coils (SSTC)]
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unrealcrafter2
April 16, 2024, 05:44:44 PM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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MRMILSTAR
April 16, 2024, 03:12:12 PM
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Re: Drsstc voltage spike question
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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unrealcrafter2
April 16, 2024, 02:28:01 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Saattvik24
April 16, 2024, 01:56:26 PM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 16, 2024, 06:50:47 AM
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Re: IKY150N65EH7, is it good for DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Anders Mikkelsen
April 16, 2024, 04:57:47 AM
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Re: IKY150N65EH7, is it good for DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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ethanwu0131
April 16, 2024, 03:40:53 AM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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flyingperson23
April 16, 2024, 01:31:17 AM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 15, 2024, 11:19:52 PM
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3D printed mini-slayer: world's weakest tesla coil
[Solid State Tesla Coils (SSTC)]
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Michelle_
April 15, 2024, 11:10:19 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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alan sailer
April 15, 2024, 11:04:19 PM
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Re: Ignitron trigger drive ideas?
[Capacitor Banks]
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Twospoons
April 15, 2024, 11:02:05 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 15, 2024, 10:57:59 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 15, 2024, 10:55:46 PM
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Re: Return of Electronics Flea Market in "Silicon Valley"
[Sell / Buy / Trade]
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klugesmith
April 15, 2024, 10:37:32 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Saattvik24
April 15, 2024, 10:05:00 PM
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Re: How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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MRMILSTAR
April 15, 2024, 09:28:50 PM
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Ignitron trigger drive ideas?
[Capacitor Banks]
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klugesmith
April 15, 2024, 09:06:42 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Mads Barnkob
April 15, 2024, 08:46:32 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Benbmw
April 15, 2024, 08:38:39 PM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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sky-guided
April 15, 2024, 08:23:40 PM
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How to get a GE Yokogawa AB40 Sync Scope to rotate without a powerplant.
[Laboratories, Equipment and Tools]
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Bobakman
April 15, 2024, 06:43:23 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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flyingperson23
April 15, 2024, 06:29:10 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 15, 2024, 05:21:53 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 15, 2024, 05:15:33 AM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 15, 2024, 04:07:54 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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davekni
April 15, 2024, 03:49:03 AM
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Re: Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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alan sailer
April 14, 2024, 09:46:30 PM
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Small-ish 3D printed SGTC via cheap ZVS flyback build, humbly asking a couple ?s
[Spark Gap Tesla Coils (SGTC)]
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Michelle_
April 14, 2024, 07:31:00 PM
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Re: First DRSSTC SKM100
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Saattvik24
April 14, 2024, 02:26:19 PM
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Re: mg75q2ys40 IGBT
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Mads Barnkob
April 14, 2024, 07:20:54 AM
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Re: IKY150N65EH7, is it good for DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Mads Barnkob
April 14, 2024, 07:18:20 AM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 13, 2024, 06:46:40 AM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 13, 2024, 04:18:42 AM
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Re: Upper and Lower Explosive Limits on Confined Flammable Vapors at -79 C.
[General Chat]
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alan sailer
April 13, 2024, 03:24:20 AM
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Re: Game changing tesla coil secondary winding suggestions
[General Chat]
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alan sailer
April 13, 2024, 03:20:46 AM
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Game changing tesla coil secondary winding suggestions
[General Chat]
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Michelle_
April 13, 2024, 03:13:22 AM
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Re: Capacitor Blowout
[Sell / Buy / Trade]
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lbattraw
April 12, 2024, 09:14:58 PM
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mg75q2ys40 IGBT
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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thedark
April 12, 2024, 08:40:18 PM
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Re: UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 12, 2024, 07:20:30 PM
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Re: Mosfet Buffer Stage Questions
[Beginners]
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davekni
April 12, 2024, 07:12:43 PM
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IKY150N65EH7, is it good for DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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ethanwu0131
April 12, 2024, 04:47:33 PM
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Re: UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Admiral Aaron Ravensdale
April 12, 2024, 11:43:36 AM
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Mosfet Buffer Stage Questions
[Beginners]
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Egg
April 12, 2024, 12:49:02 AM
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Re: UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 12, 2024, 12:41:16 AM
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Re: Plasma Torid - Class E Self Resonant Dual/Stereo - Plasma Torid Build
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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davekni
April 12, 2024, 12:22:41 AM
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Re: Capacitor Blowout
[Sell / Buy / Trade]
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Michelle_
April 11, 2024, 10:45:53 PM
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Re: UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Admiral Aaron Ravensdale
April 11, 2024, 07:39:30 PM
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Re: UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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flyingperson23
April 11, 2024, 07:24:52 PM
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Re: Tesla coil safety questions, risk analysis quantified
[Beginners]
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sky-guided
April 11, 2024, 06:09:30 PM
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UD 2.7 OCD LED stays on, no output during inital test
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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Admiral Aaron Ravensdale
April 11, 2024, 12:55:16 PM
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Re: Plasma Torid - Class E Self Resonant Dual/Stereo - Plasma Torid Build
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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alan sailer
April 11, 2024, 03:40:00 AM
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Re: Plasma Torid - Class E Self Resonant Dual/Stereo - Plasma Torid Build
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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sky-guided
April 11, 2024, 03:05:07 AM
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Re: Tesla coil safety questions, risk analysis quantified
[Beginners]
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Michelle_
April 11, 2024, 02:57:33 AM
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Re: Tesla coil safety questions, risk analysis quantified
[Beginners]
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alan sailer
April 11, 2024, 01:44:32 AM
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Re: Tesla coil safety questions, risk analysis quantified
[Beginners]
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Michelle_
April 11, 2024, 01:31:40 AM
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Re: Plasma Torid - Class E Self Resonant Dual/Stereo - Plasma Torid Build
[Dual Resonant Solid State Tesla coils (DRSSTC)]
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OmGigaTron
April 11, 2024, 01:11:00 AM
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Re: Tesla coil safety questions, risk analysis quantified
[Beginners]
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alan sailer
April 11, 2024, 12:58:52 AM
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