Looks like duty cycle adjustment has no effect.  Perhaps 100k POT to the right of right 555 is the wrong value or shorted.
Also, did you change which side of 12V transformer is being scoped for line voltage reference?  Does not match previous plot of pin 3.

Looks good, other than noise.  What does this look like with horizontal expanded as much as possible, say 10ns/div or how ever fast your scope can go?  The noise is likely so high frequency that it is aliasing with scope sample frequency.  I'd guess either you are near some RF communication equipment or a part on your board is oscillating at high frequency (driver chips would be most likely for that).

Ideally self-oscillation frequency will be close to operating frequency, about 3x higher than now.  330pF would be roughly there.  However, better to go down to 220pF and increase R13 value to get back down to 450kHz.  Better to have some margin away from self-oscillation dropping out.  (Likely going to very high frequency rather than dropping out, too high to get through driver chip.  Could cause problems, so better to stay away from failure threshold.)

Yes.  I recommend a lower value such as 1k instead of 100k.  As low as you have around without exceeding power dissipation limit of resistor.  That will reduce sensitivity to both diode bridge leakage current or noise.

TiagoBS,
Were you able to implement the components that I shared in my previous post? I added an updated screenshot as well. I ended up using a 220pf cap and a 11k resistor to get the correct oscillation frequency. 1nf should work it is just a matter of choosing the corresponding resistor value to achieve the desired freq.

I can't quite read the low-res schematic image from LabCoatz.  The resistor on AC input after 1N4148 diode looks like perhaps 100k.  That may be too high if diode bridge has much leakage current.  I'd replace with 1k or lower and then scope again.  Diode leakage current and minimal load may be causing your line timing issues.

Why were you not able to measure the interrupter output?

The only other thing I can think of at the moment is related to the ZCD

If I'm understanding your pictures correctly, one issue shows up there:  Shield for driver should be connected to ground including driver ECB ground.  Bottom of secondary should not connect to shield, not until after passing through CT.

Noise is unexpected.  Is the H-bridge powered for this measurement of 74HC14-4?  Or is this with only logic powered?

That is more different than I'd expect, but perhaps reasonable.  74HC14 input threshold voltage is usually a bit below 2.5V (below half of supply voltage).  Your chips must be quite a bit below 2.5V.  Are you certain your chip isn't 74HCT14?

This duty cycle error (not 50%) can be fixed by adding another resistor, either across D2 or from 74HC14-1 to ground.  That lowers the input signal level to be centered around 74HC14 input logic threshold.  Resistor value needs to be adjusted to get 50% duty cycle.

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The other one I wound around a ferrite core I took from an old computer power supply (about 55 turns).

How do you know this core is ferrite?  Most supply toroid cores are powdered iron (or iron alloy).  The input line common-mode choke core will be ferrite, if that is what you pulled from supply.  Other cores are likely not ferrite and not suitable for CTs.
Any picture with CT actually connected?

Are you back to FET now?  Thought you'd changed to FGA60N65SMD IGBT.

I'd be amazed if a neon lamp made any significant contribution to SSR load.  Generally requires an incandescent lamp of at least 5 watts.  You may be lucky enough that your coil circuit is drawing sufficient power at low voltage to keep SSR operating properly.

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So, using a higher value for C would be bringing the primary impedance down, in this case, when using 68nF the impedance would be close to 2ohms, which I believe is bad for the IGBT, right?

Changing capacitance across IGBT changes both impedance and primary resonant frequency.  Frequency is defined by where impedance of L and C match.  Your calculations show mismatched impedances, so not at resonance.  Normal DRSSTCs usually start with primary frequency below secondary.  Many QCW coils start with primary frequency slightly above secondary to force initial upper-pole operation.  (Research coupled resonant circuits here or other internet places.  TC primary and secondary circuits are two coupled resonators.)

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Is there any way to calculate the primary impedance "ideal" range in relation to the IGBT/MOSFET used, or is it just from experimentation?

Yes, 2 ohms is probably too low for your circuit.  For this class-E circuit, impedance is roughly peak Vce / peak Ice.
BTW, added Cce is in parallel with IGBT's internal Cce.  Use total for resonant calculations.

For this class-E circuit, impedance is roughly peak Vce / peak Ice.

Another way to look at class-E circuits such as this:  The drain (collector) waveform consists of only relatively-wide "spikes" that form the resonant waveform.  These "spikes" are the top part of a sine-wave.  The remainder of the sine wave is clamped to ~0V by FET/IGBT conduction.  If the "spike" voltage is too high, then the resonant capacitor (the drain-source or collector-emitter capacitor) needs to be increased to widen the "spike" and thus lower its peak voltage.  Or, operating current needs to be reduced to reduce spike voltage.