High Power / High Freq. IGBT Gate Driver

[dannybeckett]

Hi guys, designing a gate driver to attempt QCW on some Infineon IGBT bricks.

I don't want the drive current / voltage to limit my testing, so I'm over-enginering the drive circuitry for this purpose. It's a modifcation of NEYi's SimpleDriver:

https://highvoltageforum.net/index.php?topic=525.0
https://tqfp.org/simple-tesla/simpledriver-v23-in-english.html
https://bsvi.ru/projects/SimpleDriver2/SimpleDriver_2.3.pdf

One UCC27424 drives two FDD8424H, each containing a p and n type mosfet. The outputs of the intermediate mosfets are paralleled, and feed the gate of the IGBT brick (the simulated IGBT here is only a small device, struggling to find a SPICE model of a big brick). Feed frequency is 500 kHz 50% duty.

The nice aspects of this design are:

• High frequency gate drive
• High instant drive current
• High continuous power to facillitate high freq gate drive
• 220n caps allow for floating gates to allow any (within reason) brick gate drive voltage

I know there's additional circuitry required to finish off the driver, but interested to get feedback from a theory POV!

[dannybeckett]

Couple more simulations with artifically-enlargened gate (copied capacitance from FF300R12KS4 datesheet), demanding more drive power. Gate waveforms look wobbly due to additional caps. Would like to know how to flatten out those curves!

[davekni]

(the simulated IGBT here is only a small device, struggling to find a SPICE model of a big brick)

I've had trouble with IGBT simulation models too.  However, since you have one that works, can you add a scaling parameter to the instance?  At least for LTSpice, adding a parameter m=10 for example will scale the model as if there were 10 paralleled devices.  Works for any model AFAIK.  I use it mostly for FETs.  I think "m" stands for multiplier.

Would like to know how to flatten out those curves!

Looks like FETs are being driven at +-7.5Vgs.  Would get a little lower Rds-on at 10Vgs.
Most of the bumps are due to 2-ohm gate resistance (R1).  Gate resistance is intended to slow down transitions.  Bumps in Vge are exactly how transitions are slowed.  If you want faster transitions, reduce R1 value.  However, will require very low parasitic inductance to work well with fast transitions.  Might be helpful to scan through my low-inductance tutorial posts:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

[dannybeckett]

can you add a scaling parameter to the instance?

Really nice feature that but TINA doesn't support it. I did copy paste 12 devices in parallel though, switching waveforms were perfect and Ig only reached a peak value of ~1.5A, so I decided to keep those model parastitic capacitors instead, taken from the IGBT module datasheet.

Looks like FETs are being driven at +-7.5Vgs.  Would get a little lower Rds-on at 10Vgs.

The FETs see a Vgs of 15V - the max voltage you'd want to use with the UCC27424. DC is blocked, so the FET gate voltage is allowed to drift to the voltage it needs, to switch the +21 / -9 V into the gate of the IGBT

Most of the bumps are due to 2-ohm gate resistance (R1).  Gate resistance is intended to slow down transitions.  Bumps in Vge are exactly how transitions are slowed.  If you want faster transitions, reduce R1 value.  However, will require very low parasitic inductance to work well with fast transitions.  Might be helpful to scan through my low-inductance tutorial posts:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

This is very valuable information, copper foil is a really good idea! I will build the bridge paying careful attention to parastitic inductance - I may have worried only about the high power side if not for this post. And indeed, reducing R1 did speed up the switching and lessen the bumps. Am I in danger of burning out the IGBT gate with a value of R1 that's too low?

I've made some changes to the design below:

• Wired p-channel FETs to OUTA
• Wired n-channel FETs to OUTB
• Used SN74HC04 as a fixed delay of ~85 ns, to maybe prevent shoot-through current (never seen this before, wonder if it'll work?)

Thinking it's about time to stick on a PCB and do some bench testing?

[davekni]

The FETs see a Vgs of 15V - the max voltage you'd want to use with the UCC27424. DC is blocked, so the FET gate voltage is allowed to drift to the voltage it needs, to switch the +21 / -9 V into the gate of the IGBT

Now that you have added diodes across FET g-s leads, this is accurate.  Before, if you ran simulation long enough for R/C time constant to settle, Vgs would settle to +-7.5V.
15V is high for Vgs.  Will cause significant cross-conduction of FETs during switching, dissipating excess FET power and pulling large switching current spikes from supplies.  Bypass FET supplies very well if staying at 15V.  UD2.7 uses 9V for this reason.  I just yesterday changed one of my similar boards from 12V to 9V to reduce FET power in a 450kHz QCW application.

Am I in danger of burning out the IGBT gate with a value of R1 that's too low?

Two possible issues.  First is maintaining sufficient dead time.  R1/SD5 add dead time.  Low R1 reduces added dead time.
Second is avoiding Vce voltage spikes above Vce rating.  Even with good H-bridge construction, there is some internal IGBT inductance and diode forward-recovery time.
If hard-switching turn-on, then diode reverse recovery is also an issue.  Very-fast turn-on will cause opposite diode reverse recovery at high current, leading to a voltage spike as diode recovery time ends.

Used SN74HC04 as a fixed delay of ~85 ns, to maybe prevent shoot-through current (never seen this before, wonder if it'll work?)

I think this is fixing shoot-through on one edge and making it much worse on the other edge.  (There is a thread here doing something similar in a GDT-connected system for adding dead-time to H-bridge IGBTs.  That works because GDT input is 0V at both edges during delay time.  GDT leakage inductance is more problematic with that setup, however.)

[dannybeckett]

Agh, you're right..... I was wondering what those diodes were there for actually, I just lifted them from the aforementioned design (in first post) without figuring out what they did yet. Was going to work that out next, but you've solved that mystery for me, thank you. I understand now that you mean +/-7.5 around the IGBT gate drive voltages (21 and - 9 V). Nice!

OK, thanks for the advice around FET gate drive voltages. My thinking was to drive them as hard as possible to maximise switching speed but I will adjust to 9 V (plenty anyway).

So dead time, are you referring to time where the gate has no current flowing through it? I'd like to proto this thing and work out all these problems before moving onto the high power IGBT section.

And yes you're right, the fixed delay fixes shoot through on the rising edge transitions and makes it way worse on the falling. I quite like the separate p chan / n chan FET control in this schema, so I'll think a little more on how to make that work.

[dannybeckett]

This is pretty lame but thinking along the following lines. A better approach would be to implement a proper variable delay line:

https://www.digikey.co.uk/en/products/detail/analog-devices-inc-maxim-integrated/DS1023S-200/1196576

An unintended benefit is the duty cycle of the IGBT looks closer to 50% now:

[davekni]

A better approach would be to implement a proper variable delay line:

No need for anything that precise and expensive, especially for a hobby project where a value can be tweaked as needed.  A simple series R followed by C to ground into a schmitt-trigger input gate (or inverter pair or buffer) should be fine.  For a bit more delay stability, add L in series with R with value to form critically-damped LRC circuit.

An unintended benefit is the duty cycle of the IGBT looks closer to 50% now:

Yes, proper matched dead time for the FETs makes duty cycle accurate.  However, that circuit is momentarily shorting input voltage through two diodes to final HC04 output.  Better (and simpler) to use gates for logic.  Add a single delay circuit to input signal.  Use AND gate of direct and delayed input for NFET gate drive.  Use OR gate of direct and delayed input for PFET gate drive.

[dannybeckett]

Yeah you're right, it's overkill. I'll test the AND / OR schema and share simulation results. Critically damped RLC is a nice touch, thanks for the guidance Dave I appreciate it.

Dan

[dannybeckett]

OK, your schema works great Dave; I've added a few extra bits to fine tune the FET behaviour too. Amazed at how much control there is now:

• Independent rising / falling edge delay
• Duty cycle
• Dead time

I did initally use an LRC network, it works beautifully at one time constant but obviously becomes over / underdamped when varying. Might add a smidge of hysteresis in the comparators for safety.

[davekni]

Might add a smidge of hysteresis in the comparators for safety.

Yes, I rarely use a comparitor without adding hysteresis.
If intending this circuit for QCW (higher frequency than you simulations) a faster comparitor is likely necessary.
If it were my design, I'd use a single delay circuit rather than two.  Allows turn-off edge to be as fast as possible (just chip delays).  Any additional turn-off delay will need to be undone with lead compensation.  With single delay, adjust dead time with delay R/C values, and adjust duty cycle by threshold voltage (center supply for 50%).

[dannybeckett]

You're referring to the IGBT turn-off edge right? I.e. the rising edges in the waveform data. Having just one delay in this schema will adjust both turn-on and turn-off equally (graph 1 in previous post). If one of the goals is to have the IGBT turn-off faster than the turn-on, then being able to adjust both delay paths enables you to do that (see the 2nd waveform picture in post). I also quite like the idea of keeping both comparators in both signal paths to even up the propagation delays. Additionally, this is what enables the duty cycle adjustment, even when they're both set to the same time constant.

Yes that current comparator is slow, I just picked one that was in the simulator's library. And noted r.e. the speed, I'm simulating at 1 MHz now which would be good for a 500 kHz bridge - thanks for the heads up, I'd have fallen for that one. FYI this is my first power switching project so apologies if I'm not following you properly

Thanks as always for the guidance!

[davekni]

With single delay, adjust dead time with delay R/C values, and adjust duty cycle by threshold voltage (center supply for 50%).

Having just one delay in this schema will adjust both turn-on and turn-off equally (graph 1 in previous post).

To be more clear, I should have said that adjusting threshold voltage of the single comparitor will adjust rising-edge dead time relative to falling-edge time.  That would be more accurate than saying duty cycle.

You mentioned QCW application in initial post.  For most such resonant feedback applications, minimal total delay is important (delay through all circuitry from feedback input to H-bridge voltage output).  Other open-loop applications are not sensitive to total delay.  Since your simulations are open-loop so far, you will not see any disadvantage to using two comparitors.  You can see the effect as delay from input signal to H-bridge output, but it doesn't cause any problems in open-loop designs.

[dannybeckett]

I'm with you now - an important design consideration is propagation delay through the entire control system when driven closed loop, especially for QCW operation.

The following article references this delay and provides some form of compensation for it (under "phase correction"):

https://tqfp.org/simple-tesla/simpledriver-v23-in-english.html

I've found some reasonably priced 4.5 ns comparators and 2 ns gates to use... Given the FET driver has a delay of 25 ns and the IGBT module has turn on and turn off delays of 100 and 500 ns respectively, the effect of the extra comparator will be negligible (especially when R is close to 0 in the RC filter). I'm hoping that driving the IGBT gate hard will reduce the delays a bit but we'll see when bench testing. Perhaps one could leverage this technique to equalize the turn on and turn off propagation delays, so that "bulk" phase compensation features work more effectively.

One other consideration that came to mind - due to the high edge speeds, the signal paths might become transmission lines, necessitating impedance control

[davekni]

IGBT module has turn on and turn off delays of 100 and 500 ns respectively

I think there are some bricks faster than 500ns.  However, bricks are generally slow.  I'm not aware of any QCW designs using bricks.  Usually FETs (SiC for best speed) or fast TO247 IGBTs.  Bricks may work, however.  Large heat capacity may make up for less efficient switching.

I'm hoping that driving the IGBT gate hard will reduce the delays a bit but we'll see when bench testing.

Yes, most bricks are specified with significant external gate resistance.  Driving gates harder will increase speed.  Fast switching will make low-parasitic-inductance critical for H-bridge layout.

One other consideration that came to mind - due to the high edge speeds, the signal paths might become transmission lines, necessitating impedance control

Yes, need either short traces or impedance control and termination.  For single-ended (not differential) logic, series termination is easier and lower power.  However, series termination works only when received by a single chip or by a couple closely-spaced chips.  For higher-fanout signals, use multiple series resistors at source and multiple traces, one for each series resistor going to closely-grouped loads.