Author Topic: Ramped SSTC - Power Supply Question + General Improvements  (Read 5469 times)

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #40 on: May 27, 2023, 11:25:36 PM »
Quote
"Scrolling effect" sounds more like a problem with Arduino code than with input signal processing.  I'd guess the AC input pin is being sampled to infrequently.

Here is a video to show what is happening:

Yellow= Arduino Interrupter output
Blue= ZCD output (going into the input of the Arduino)
Purple= reference AC signal from small transformer
/>

I added a simple ZCD circuit (a single 2n3907) that now feeds a square wave into the input pin of the Arduino. That seems to have allowed me to get ever so slightly closer to zero crossing since the arc length has improved a bit. The remaining issue now is that scrolling/jitter (not sure what to call it). You can see from the video that it scrolls and then resets. Because the interrupter output has that slight degree of fluctuation or jitter, it's difficult to synchronize it accurately. I've been attempting to fine-tune the timing so that I hit that sweet spot where the coil won't output, will output , or will output but with shorter, more branched arcs.

As for the code, I used ChatGPT 4 to create it. I do not have any coding experience but I do have an oscilloscope, determination, and a dream. After a few failed attempts at creating a ZCD/synced output from scratch I used the code that LoneOceans created here https://www.loneoceans.com/labs/sstc4/StaccatoAttiny.ino. The piece I was missing is the fire() portion. I bashed that together with what I had created so far to match my inputs/outputs and I got this:

My code here: UNFINISHED This likely contain erroneous notes and text from using ChatGPT. The goal is to eventually review the code and clean everything up.

I can adjust the BPS and PW with two separate potentiometers. The phase delay pot was necessary to get the output to line up closer to the zero crossing. Without it the phase is off by a bit.

#define TRIGGER_PIN A0
#define OUTPUT_PIN 5
#define LED_PIN 3
#define POTENTIOMETER_PIN_BPS A1
#define POTENTIOMETER_PIN_PW A2
#define POTENTIOMETER_PIN_DELAY A3
#define POTENTIOMETER_SCALE 10

int bps = 0.5;
int pw = 4000;
int delayUs = 0;
int phaseDelayUs = 0;
bool triggerState = false;
bool triggerActive = false;

void fire();

void setup() {
  pinMode(OUTPUT_PIN, OUTPUT);
  pinMode(LED_PIN, OUTPUT);
  pinMode(TRIGGER_PIN, INPUT);
}

void loop() {
  int bpsReading = analogRead(POTENTIOMETER_PIN_BPS);
  int pwReading = analogRead(POTENTIOMETER_PIN_PW);
  int triggerReading = analogRead(TRIGGER_PIN);
  int delayReading = analogRead(POTENTIOMETER_PIN_DELAY);

  bps = map(bpsReading, 0, 800, 1, 40);
  pw = map(pwReading, 0, 1023, 1000, 9000);
  bool currentTriggerState = triggerReading > 512;

  if (!triggerState && currentTriggerState) {
    triggerActive = true;
  }

  triggerState = currentTriggerState;

  if (delayReading > 0) {
    delayUs = delayReading * POTENTIOMETER_SCALE;
    phaseDelayUs = delayUs;
  }

  if (triggerActive) {
    fire();
    triggerActive = false;
  }
}

void fire() {
  unsigned long periodMs = 1000 / bps;
  unsigned int onTimeUs = pw;
  unsigned long offTimeMs = periodMs - (onTimeUs / 1000);

  unsigned int delayCorrection = onTimeUs + phaseDelayUs;
  if (delayCorrection > periodMs * 1000) {
    delayCorrection = periodMs * 1000;
  }

  delayMicroseconds(delayCorrection);
  digitalWrite(OUTPUT_PIN, HIGH);
  digitalWrite(LED_PIN, HIGH);
  delayMicroseconds(onTimeUs);
  digitalWrite(OUTPUT_PIN, LOW);
  digitalWrite(LED_PIN, LOW);
  delay(offTimeMs);
}

The setup works for the most part besides the skipped pulses and jitter. Since I am using pots for the controls once I tune it where I want it it keeps that configuration even after a restart. I feel like I can get more performance out of the coil if I could reduce the variance in the output and get the coil to trigger closer to the zero crossing.

Quote
Yes.  Given fixed value of 5.6k, will reduce voltage faster that way, across C18.

This time around I focused more on the Interrupter but I did scope the output and saw that the spikes are still there. I will eventually test it with a resistor added to C18.

Final note, I have noticed the coil seems to have not killed itself when a flashover from the primary to secondary occurs. I have been a lot more careful with my adjustments but so far several strikes have happened when I have it adjusted too close. I wonder if the flashovers were interfering with my old opto style ZCD/interrupter which would subsequently cause a high frequency oscillation to occur that destroyed the bridge.
« Last Edit: May 27, 2023, 11:27:41 PM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #41 on: May 30, 2023, 01:58:34 AM »
Quote
Here is a video to show what is happening:

Yellow= Arduino Interrupter output
Blue= ZCD output (going into the input of the Arduino)
Purple= reference AC signal from small transformer
Clearly an Arduino timing issue, probably low sample rate as I'd initially guessed.

Quote
As for the code, I used ChatGPT 4 to create it.
I'm surprised that any functioning code was generated by ChatGPT.  My thought is to either avoid Arduino or learn how to code it yourself.
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #42 on: May 30, 2023, 04:58:50 AM »
Quote
Clearly an Arduino timing issue, probably low sample rate as I'd initially guessed.
After messing with it a bit and reading up on Arduino jitter I think the issue is more nuanced and above my basic level of understanding. I did have some success in removing the delay potentiometer, as well as a multitude of other suggestions. I found when adjusting the delay that I could get the jitter to stop completely. After updating the code it appears to be working within an expectable range. So much so I can't tell when listening to the output.

Quote
I'm surprised that any functioning code was generated by ChatGPT.  My thought is to either avoid Arduino or learn how to code it yourself.
It did a good job. It was really quick to implement changes and when it made mistakes I could tell it "There is no output" and it would realize it made an error and update the code. I could then verify it was working via the oscilloscope and I was on my way.

I did a bunch of testing, here are my results:


Resistors across DC Bus caps (C19&20)
  • without any resistors I saw a spike of ~56V @ around 100VAC input
  • There was a louder snapping/popping with the arc
Yellow=Interrupter pulse
Blue=Primary Output




  • With a 4.7kohm resistor (1/4w) across C19&20
  • Quieter arc, no snap
  • voltage spike reduced to ~22V




Resistor across AC input capacitor (C18)

  • 4.7kohm 1/4w got way too hot. Paralleled two 1/4w 11kohm resistors instead
  • voltage spike almost completely gone
  • Need to replace with a higher wattage resistor at some point





Changes to Arduino Code and ZCD

  • Added 100k bias resistor to the base of the ZCD transistor - no change
  • I can control the phase by adjusting the pot (burden resistor I guess...?) I have on the output of the AC signal transformer
  • Removed bits of code that might cause delays in the output. Implemented direct port manipulation for faster response from the Arduino
  • Much less jitter in the output signal now. Not apparent via the output sound or skipped pulses - YAY!

Auto/Self Oscillation Mod

Yellow=Interrupter pulse
Blue=Gate/Source

  • Added 1M pot from pin 2 -> C3/R1
  • High resistance values over ~300kohm resulted in no oscillation
  • measured the output and how close it was to ZC, tuned the pot value for the best performance = 18kohm
  • soldered 18kohm in place

Gate/Source pic - you can see the small chirps the driver was outputting due to the 18k resistor



Here is the primary output during self oscillation - there is a brief turn on and then off off again before the coil outputs an arc.



Without Self Oscillation

  • Without the 18k resistor the coil had virtually zero output. Every once and awhile it would have a small arc.
  • Bringing my hand close to the GDT would cause the coil to run, I assume it was picking up on the 60Hz mains via my hand

Here are a couple pictures of an arc I captured when it was triggering intermittently

Gate drive input, starting and then stopping again


Drain/Source output



Arc Appearance Questions

Secondary Fres = ~470Khz, well within range of sword arcs

The output seems to be consistently forked, like a 'V' shape from the break out instead of a long straight arc. Adding a bigger top load causes more branching and lower Fres. Every 5-6 arcs I will get a nice straight one. Any advice on what might cause the splitting so consistently?

I feel like it has to do with when the coil is starting. If there is too much voltage present when it starts could the arc be splitting instead of staying as a single arc channel? That would coincide with my slightly variable timing on the ZCD/Arduino output.


Miscellaneous Observations

  • Smaller coils with thinner wire (41awg is what mine is) are more prone to primary/secondary flash over. I assume this is due to high voltage per turn being induced into the secondary
  • When adjusting the primary coil height (usually with a smaller coil) if it is too low the arc will make a screeching sound as the variac voltage approaches full mains AC. Raising the primary up a millimeter at a time and checking until the sound goes away results in the best output. Any further and a flashover will likely occur!
« Last Edit: June 02, 2023, 08:45:48 PM by ZakW »

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #43 on: June 01, 2023, 02:05:59 AM »
More Testing!

I was able to get a lot more performance out of my coil by reducing the DC blocking capacitor value (C19&C20).

Here it is running with 0.47uf instead of 1uf. Hitting 18in at times with a 2in secondary.

/>


1uf was my base line for testing but I also tested 2uf and 1.68. All together I tested from 2uf, 1.68, 1, 0.47,0.2uf The lower the cap value the better the output. 0.2uf was causing the variac to thump/knock loudly (assuming that is a result from high peak current draw?). I was worried to push it to full mains voltage. Plus the coil output was getting very long and erratic for my small bench area and was starting to arc to everything.

I ended up going with some 0.47uf WIMA caps that I felt provided a decent improvement and a good balance between performance and stress on the inverter.

I was under the assumption per Mads write up https://kaizerpowerelectronics.dk/tesla-coils/sstc-design-guide/ that the lower the reactance the better? Higher DC blocking cap value = lower reactance...

Per Mads "Being 5 times lower than the resonant frequency, there is no risk at the primary LC circuit resulting in a DRSSTC condition which would destroy the MOSFETs." some quick calculations shows my primary Fres to be around 220kHz, with my secondary running around ~400kHz. Is this why I am seeing such a boost in the output?

Does higher impedance also play a part? I read that QCW coils tend to have higher impedance primaries.



« Last Edit: June 01, 2023, 02:36:05 AM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #44 on: June 01, 2023, 04:18:52 AM »
Quote
Much less jitter in the output signal now. Not apparent via the output sound or skipped pulses - YAY!
Glad that bit is working well.

Quote
The lower the cap value the better the output. 0.2uf was causing the variac to thump/knock loudly (assuming that is a result from high peak current draw?). I was worried to push it to full mains voltage. Plus the coil output was getting very long and erratic for my small bench area and was starting to arc to everything.
My guess:  This might be an interaction of self-oscillating and primary resonance with 0.2uF.  At least one scope capture shows 238kHz self-oscillation.  Might be close enough to primary resonance to start oscillation at that frequency instead of intended secondary resonant frequency.
Unless you make the other changes I'd suggested (CT burden resistor, much smaller value for 0.1uF input capacitor), self-oscillation frequency is likely to be unstable.  I'd suggest either going back to 1meg just to bias 74HC14-1 to center-supply, or make other changes.

Quote
The output seems to be consistently forked, like a 'V' shape from the break out instead of a long straight arc. Adding a bigger top load causes more branching and lower Fres. Every 5-6 arcs I will get a nice straight one. Any advice on what might cause the splitting so consistently?

I feel like it has to do with when the coil is starting. If there is too much voltage present when it starts could the arc be splitting instead of staying as a single arc channel? That would coincide with my slightly variable timing on the ZCD/Arduino output.
Too much initial voltage, or perhaps initial start at wrong frequency due to self-oscillation too low, or perhaps not starting at all initially then starting after voltage is a bit too high.  Fixing self-oscillation to be stable would fix latter two of three guesses.  Or delay enable edge until voltage is a bit higher (not counting remaining voltage from previous half-cycle) so that feedback oscillation starts immediately and remains on.  (Perhaps counterintuitive, but a bit more delay in enable start might help.)
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #45 on: June 01, 2023, 08:39:13 PM »
Quote
My guess:  This might be an interaction of self-oscillating and primary resonance with 0.2uF.  At least one scope capture shows 238kHz self-oscillation.  Might be close enough to primary resonance to start oscillation at that frequency instead of intended secondary resonant frequency.
Sorry I was not more clear. The testing I did with different DC blocking capacitor values was independent of all the previous scope shots.

When I was testing with 0.2uf for each cap, the primary output voltage was significantly higher than when I used larger cap values. The output of the coil was very impressive but I wanted to dial it back before I broke something. I also wanted to conduct more testing to make sure I was staying within the parameters of the IGBTs. I can post some measurements of the primary output with the current 0.47uf caps as well as after I add some 1uf caps to bring the total to 1.47uf for comparison. Because I saw an increase in the output of the coil, presumably an increase in primary current I was not sure if I was approaching a potential primary resonance issue that might destroy the bridge.

Quote
Unless you make the other changes I'd suggested (CT burden resistor, much smaller value for 0.1uF input capacitor), self-oscillation frequency is likely to be unstable.  I'd suggest either going back to 1meg just to bias 74HC14-1 to center-supply, or make other changes.

I think the coil feedback is working with the addition of the 18k resistor. It seems very consistent and is not skipping pulses or snapping erratically. I am happy to explore your suggestions with the lower cap value and additional burden resistor to see if I can get any better results.

Quote
Too much initial voltage, or perhaps initial start at wrong frequency due to self-oscillation too low, or perhaps not starting at all initially then starting after voltage is a bit too high.  Fixing self-oscillation to be stable would fix latter two of three guesses.  Or delay enable edge until voltage is a bit higher (not counting remaining voltage from previous half-cycle) so that feedback oscillation starts immediately and remains on.  (Perhaps counterintuitive, but a bit more delay in enable start might help.)

Great suggestion - I did notice that while increasing the voltage via the variac I get much straighter arcs around ~90V AC. Once I hit full mains voltage (120V) they start to split in that V shape. I will mess around with the self-oscillation to see if that corrects the issue.




Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #46 on: June 02, 2023, 03:53:33 AM »
Update: Hit 20inches!! That is a personal record  ;D 10x the secondary length

/>

Changes:
  • Added 1k burden resistor across CT input
  • Lowered C3 from 100nf to 1nf. That was a bit of trial and error while using the 1Meg pot.
    • Lower the cap value the higher the oscillation frequency
  • Measured the pot value right before oscillation cut out (at its highest frequency), 8.6k ohm. Installed an 8.2k ohm resistor from pin 2 to C3/R1

Those changes had a significant impact on the arc straightness. The burden resistor made the signal much neater and more square, while the new cap/resistor pair value oscillation frequency is now much higher than before. Somewhere around ~250kHz I think. There does not appear to be a gap at the start of the coil turning on now, likely allowing the arc to start forming earlier in the cycle.

  • Added a slightly larger diameter metal disc, that also improved arc straightness
    • Anything larger and the arcs start branching a lot. The load from the output is bringing the frequency down below 400kHz. I am going to wind a new secondary coil with a higher Fres so I can add a larger top load to help stabilize the output without lowering the frequency too much.
  • Primary height now has an impact on arc appearance.
    • Too high = long but erratic and splitting
    • Too low = splitting and shorter
    • Middle = straightest and longest

    Here are some scope shots of the primary output with 0.2uf DC blocking caps installed.
    Blue = Primary output



    For comparison, here is the output with 0.47uf caps which is what is currently installed and working the best.






    Is the output waveform supposed to look like that?



    I decided to remove a couple components as well: All in the name of the longest arc

    • C18 (1uf) across the Mains input - decreased output slightly and caused a loud snapping sound in the arc. A bleeder resistor helped but also decreased output
    • C18 bleeder resistor - slightly decreased output
« Last Edit: June 02, 2023, 04:10:31 AM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #47 on: June 02, 2023, 07:19:37 PM »
Quote
Lowered C3 from 100nf to 1nf. That was a bit of trial and error while using the 1Meg pot.
Looks like C3 in the range of 220pF to 470pF would be good, allowing self-oscillation to hit your operating frequency, around 450kHz if I recall correctly.

Quote
Is the output waveform supposed to look like that?
I'm not clear on what your input circuit looks like now and where the scope probe is connected.  Here's what I'm picturing, edited from your reply #4 image:



Is that accurate?  If not, what is the circuit?  Is scope probe on CT input (J1 pin 1)?
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #48 on: June 02, 2023, 08:31:37 PM »
Quote
I'm not clear on what your input circuit looks like now and where the scope probe is connected.  Here's what I'm picturing, edited from your reply #4 image:

Apologies, after so many updates it has gotten a bit confusing. You are spot on though. Here are some updated schematics with currently installed components. 





Quote
Is scope probe on CT input (J1 pin 1)?

The previous scope shots comparing the different cap values were taken with my differential probes connected to the bridge primary output as seen in the above bridge schematic.

For testing the self oscillation frequency I connected my differential probes to Q2 gate/source. There I was be able to see the self oscillation frequency vs when the coil was running.

Quote
Looks like C3 in the range of 220pF to 470pF would be good, allowing self-oscillation to hit your operating frequency, around 450kHz if I recall correctly.

I can try reducing it further. I did notice at some frequencies (typically much lower than what it is now) that the current draw from the driver increased to about 35mA while the bridge was off. Normally, it hovers around 13mA. I assumed this was due to the UCC tying to output constantly at the frequency of the self oscillation? It seems to have gone away at higher frequencies, figured I would mention that.

As I was writing this I grabbed a few more pictures. In them you can see the self oscillation running (~145kHz) until the coil feedback (~463kHZ) takes over. Note: coil secondary frequency is higher since this was not a full voltage test, arc loading etc...

Yellow= Interrupter output
Purple= 74HC14 Pin 4 output (self oscillation)
Blue= Q2 gate/source








So in my previous post (https://highvoltageforum.net/index.php?action=dlattach;topic=2338.0;attach=18447;image) the scope shot where I have the differential probe connected across the primary output of the bridge (0.47uf caps test), is the output waveform supposed to look like that? Sort of square-ish? The 0.2uf output looks more like a sinewave too. The output has improved drastically with the lower 0.47uf caps installed, I guess I wanted to make sure it is not killing my IGBTs to be running like that. The voltage spikes are well under 650v.


Next steps so far:
  • Try installing a smaller cap to get the self oscillation frequency more in line with the operating frequency of the coil
  • Swap out the Arduino Uno for a Nano and test the code to ensure it works the same
  • Start redesigning the PCB to accommodate all the changes I have made so far





« Last Edit: June 02, 2023, 08:49:44 PM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #49 on: June 02, 2023, 09:06:34 PM »
Quote
Apologies, after so many updates it has gotten a bit confusing. You are spot on though. Here are some updated schematics with currently installed components.
Thank you for the schematic update.  Very helpful.

Quote
The previous scope shots comparing the different cap values were taken with my differential probes connected to the bridge primary output as seen in the above bridge schematic.
Oh, that makes sense now.  With 0.2uF half-bridge caps, primary voltage swing is about 3x bus voltage, so you are getting close to primary resonance.  That explains why output increases.  Primary current is increasing too.  The step part of the waveform is half-bridge switching.  Remaining sine-wave portion is resonant voltage across 0.2uF caps.  Less when across 0.47uF caps as would be expected.

Might be ideal with a value between such as 0.33uF.  At 0.22uF, looks like half-bridge switching may be slightly past zero current.  At 0.47uF appears to be well before zero current.  Before is better than after, but just barely before is ideal.  SSTCs are not usually designed to hit ZCS conditions.  Tweaking that in would be an extra benefit compared to most SSTCs.  However, doing so requires looking carefully at the highest current/voltage portions of the half-cycle where it matters most, making sure switching doesn't get past zero-current point.

Quote
As I was writing this I grabbed a few more pictures. In them you can see the self oscillation running (~145kHz) until the coil feedback (~463kHZ) takes over. Note: coil secondary frequency is higher since this was not a full voltage test, arc loading etc...
Ideally self-oscillation frequency will be close to operating frequency, about 3x higher than now.  330pF would be roughly there.  However, better to go down to 220pF and increase R13 value to get back down to 450kHz.  Better to have some margin away from self-oscillation dropping out.  (Likely going to very high frequency rather than dropping out, too high to get through driver chip.  Could cause problems, so better to stay away from failure threshold.)  Or, if R10 is decreased, that should allow margin for lower R13.  Very-high-frequency mode is likely when the voltage divider ratio of R13 and R10 is high enough to trip 74HC14 threshold without waiting for C3 to charge.  Also, self-oscillation frequency will be more stable farther from that very-high-frequency failure threshold.

Quote
I can try reducing it further. I did notice at some frequencies (typically much lower than what it is now) that the current draw from the driver increased to about 35mA while the bridge was off.
Only guess I have is the above-mentioned very-high-frequency oscillation.  That would draw more current.  Was this with larger C3 and low R13?

Edit:  Just noticed this comment and resulting schematic change:
Quote
I decided to remove a couple components as well: All in the name of the longest arc
    C18 (1uf) across the Mains input - decreased output slightly and caused a loud snapping sound in the arc. A bleeder resistor helped but also decreased output
    C18 bleeder resistor - slightly decreased output
Likely reason removing C18 improved performance:  C18 "shorts" bridge power (what I call Vbus+) to neutral (Vbus-) for AC (450kHz) current.  That makes C19 and C20 effectively in parallel.  So removing C18 is similar to reducing value of C19 and C20.  Down side is that wiring inductance of bridge power and neutral now become a significant part of the circuit, especially if within an order of magnitude or so of primary inductance.  I'd consider putting C18 back into the circuit and lowering value of C19 and C20.  0.2uF may be fine for C19 and C20 with C18 back in place.
Yes, bleeder resistor is needed to discharge C18 (and C19/C20) between line half-cycles.  Once self-oscillation frequency is close to 450kHz, I'm guessing bleed resistor won't decrease performance as much.  If bleed is still an issue, a couple options are more effective than a plain resistor.  One is to add a large inductance such as primary of a small line-frequency transformer in series with bleed resistor.  That will keep current flowing longer as voltage approaches zero, so bleed more effectively without requiring as low a resistor value.  Another alternative is a constant-current source circuit instead of a resistor.
« Last Edit: June 02, 2023, 09:55:08 PM by davekni »
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #50 on: June 02, 2023, 10:21:50 PM »
Quote
Oh, that makes sense now.  With 0.2uF half-bridge caps, primary voltage swing is about 3x bus voltage, so you are getting close to primary resonance.  That explains why output increases.  Primary current is increasing too.  The step part of the waveform is half-bridge switching.  Remaining sine-wave portion is resonant voltage across 0.2uF caps.  Less when across 0.47uF caps as would be expected.

Might be ideal with a value between such as 0.33uF.  At 0.22uF, looks like half-bridge switching may be slightly past zero current.  At 0.47uF appears to be well before zero current.  Before is better than after, but just barely before is ideal.  SSTCs are not usually designed to hit ZCS conditions.  Tweaking that in would be an extra benefit compared to most SSTCs.  However, doing so requires looking carefully at the highest current/voltage portions of the half-cycle where it matters most, making sure switching doesn't get past zero-current point.
That makes a lot of sense now, thanks for breaking that down. I already have some 0.33uf caps in my shopping cart!

Is this what you mean by "slightly past zero current"



Quote
Ideally self-oscillation frequency will be close to operating frequency, about 3x higher than now.  330pF would be roughly there.  However, better to go down to 220pF and increase R13 value to get back down to 450kHz.  Better to have some margin away from self-oscillation dropping out.  (Likely going to very high frequency rather than dropping out, too high to get through driver chip.  Could cause problems, so better to stay away from failure threshold.)  Or, if R10 is decreased, that should allow margin for lower R13.  Very-high-frequency mode is likely when the voltage divider ratio of R13 and R10 is high enough to trip 74HC14 threshold without waiting for C3 to charge.  Also, self-oscillation frequency will be more stable farther from that very-high-frequency failure threshold.
I will lower C3 to 220pF and update R13 after I see how much margin I have via pot before the oscillation dies out. If it is not a lot I will try lowering R10.

Quote
Only guess I have is the above-mentioned very-high-frequency oscillation.  That would draw more current.  Was this with larger C3 and low R13?
That is correct, that happened when C3 was larger and R13 was lower. Doesn't seem to be an issue now, I was just curious. 

Quote
Likely reason removing C18 improved performance:  C18 "shorts" bridge power (what I call Vbus+) to neutral (Vbus-) for AC (450kHz) current.  That makes C19 and C20 effectively in parallel.  So removing C18 is similar to reducing value of C19 and C20.  Down side is that wiring inductance of bridge power and neutral now become a significant part of the circuit, especially if within an order of magnitude or so of primary inductance.  I'd consider putting C18 back into the circuit and lowering value of C19 and C20.  0.2uF may be fine for C19 and C20 with C18 back in place.
Yes, bleeder resistor is needed to discharge C18 (and C19/C20) between line half-cycles.  Once self-oscillation frequency is close to 450kHz, I'm guessing bleed resistor won't decrease performance.
Great! It is nice to understand more of C18s function and how it impacts C19 and C20. I will try reinstalling C18 and lowering C19/20 to 0.2uf again all with bleeder resistors.
« Last Edit: June 02, 2023, 10:24:00 PM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #51 on: June 02, 2023, 11:11:58 PM »
Quote
Is this what you mean by "slightly past zero current"
Not quite.  Red circles are what I'm talking about, not green "zero".  You are scoping voltage across primary coil, which is the same as across either C19 or C20 during any given half-cycle.  Zero current through capacitor is when voltage slope is zero.  Voltage is roughly flat before switching as you have circled in red.  Hard to say exactly where within that relatively-flat voltage spot current is changing polarity.  In your similar plot with 0.47uF caps, voltage is still slewing rapidly at half-bridge switching points, so current is well before zero.

BTW, at 60Hz line, there is 8.33ms between positive half-cycles, perhaps 11ms from when C18 stops charging from previous positive half-cycle.  C18 + series of C19 and C20 is 1.1 to 1.2uF depending on C19 and C20 values.  Every RC time constant voltage drops by 1/e (1/2.781828).  Three time constants gets to roughly 5% of initial voltage, probably good enough.  11ms / 3 = 3.67ms time constant, or about 3k across 1.2uF.  About 2.5W for 3k.  If 2.5W is too much, that is where current source or series inductance would help, allowing lower power and better discharge.
« Last Edit: June 02, 2023, 11:18:46 PM by davekni »
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Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #52 on: June 04, 2023, 12:13:41 AM »
Is this accurate? Made using paint so it is not pretty. I wanted to make sure I understand the waveforms and where things are occurring.



Quote
In your similar plot with 0.47uF caps, voltage is still slewing rapidly at half-bridge switching points, so current is well before zero.
By slewing rapidly, do you mean the spikes after switching? If so, do larger spikes indicate switching well before zero current? Like the IGBTs are switching off while current is flowing hence the spikes?

Quote
BTW, at 60Hz line, there is 8.33ms between positive half-cycles, perhaps 11ms from when C18 stops charging from previous positive half-cycle.  C18 + series of C19 and C20 is 1.1 to 1.2uF depending on C19 and C20 values.  Every RC time constant voltage drops by 1/e (1/2.781828).  Three time constants gets to roughly 5% of initial voltage, probably good enough.  11ms / 3 = 3.67ms time constant, or about 3k across 1.2uF.
Thank you for this. I am a bit confused by what you are suggesting - are you saying to use a single 2.5W 3k resistor across C18 or 3k total across all caps (C18/19/20) or something else?

Quote
About 2.5W for 3k.  If 2.5W is too much, that is where current source or series inductance would help, allowing lower power and better discharge.
2.5W being too much as in 3k ohm is too low allowing too much current to flow, right?

Could you elaborate on 'current source and series inductance would help'?


Testing Yesterday

I tested a lot yesterday and somehow forgot to take pictures of the scope along the way.

Self oscillation changes
  • changed C3 to 220pf - oscillating now at 450kHz
  • Made R10 11k ohms to achieve 450kHz
Bridge changes - 0.2uf
  • swapped C19/20 back to 0.2uf
  • added C18 back (1uf)
  • added 4.2k bleeders for C18/C19/20
Arcs grew very branched as I got close to 120V. I always notice really nice straight arcs around 100V. Pass that and things get branched. Lowering the primary as low as it could go on the secondary seemed to help with arc straightness. Still not as uniform as 0.47uf setup.

Bridge changes - 0.3uf

I figured 0.2uf was too little capacitance so I soldered a third 0.1uf cap to C19/C20 for a total of ~0.3uf

Messing with the primary a bit, I could not seem to get the arcs to be consistently straight either. The primary waveform looked closer to 0.47uf with smaller spikes (maybe an indication that switching was closer to zero current but still before). Slightly lower coupling and moving the primary down still seemed to help with arc appearance. Fres was now around ~350kHz. Straight arcs were having smaller arcs shoot off 90degrees around midway from the main arc (weird shape), still erratic.

A flashover from the ground end of the coil to primary killed IGBTs, even though it was not raised anywhere near where I typically experience flashovers... I have one more pair of IGBTs, working on ordering more from Mouser after this. I can take some scope shots later of to provide more information with the current configuration before I make any more changes.

I suspect the 0.1uf caps I am using for the bridge are not ideal. I ordered them awhile back and am not sure of their specs. I am going to order some WIMA caps that have seemed to work well before.




Do you have any insight into why lower primary height/lower coupling seems to promote straighter arcs?

I would like to wind an identical coil just with fewer turns to see if increasing the Fres helps with arc straightness as well.

Edit: Could the self oscillation frequency be set too high causing issues and potentially the flash over? Since the arc loading is detuning the coil so much?
« Last Edit: June 04, 2023, 12:34:46 AM by ZakW »

Offline davekni

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #53 on: June 04, 2023, 03:23:08 AM »
Quote
By slewing rapidly, do you mean the spikes after switching? If so, do larger spikes indicate switching well before zero current? Like the IGBTs are switching off while current is flowing hence the spikes?
I'm talking about just before the vertical transitions you marked in yellow.  On the right plot (0.47uF), slope after transition is close to zero as you marked in red.  Before transition, slope is reasonably steep.  Slope is starting to decrease before transition.  Glitch and ringing after transition makes it a bit harder to figure out exactly what occurs then, but roughly flat as you have shown in red.

Quote
Thank you for this. I am a bit confused by what you are suggesting - are you saying to use a single 2.5W 3k resistor across C18 or 3k total across all caps (C18/19/20) or something else?
I'm suggesting a single 3k resistor rated for 2.5W or higher across C18.  (Or could be a bit lower and higher power, such as 2.5k rated for 3W or higher.)

Quote
2.5W being too much as in 3k ohm is too low allowing too much current to flow, right?
3k is fine as long as you have a resistor capable of at least 2.5W, and the warm resistor doesn't cause thermal issues for any neighboring components.

Quote
Could you elaborate on 'current source and series inductance would help'?
Only reason to consider these is if 2.5W is too much heat.  These two alternatives can discharge C18 while generating less heat.  Down side is complexity.

Quote
Edit: Could the self oscillation frequency be set too high causing issues and potentially the flash over? Since the arc loading is detuning the coil so much?
Certainly a possibility. I was wondering about that as soon as you mentioned running at 350kHz.

All this experimenting with relatively low primary capacitance is getting you close to dual-resonant coils.  There are always two resonances, even in normal SSTC designs.  Lower resonance (called lower pole) is normally far below normal SSTC operating frequency of upper pole.  Reduced primary capacitance moves lower pole closer to upper.  Boosts primary current and therefore performance as you have seen.  However, also makes it possible to lock to either frequency.  Rather than continuing with semi-random experimentation, I'd suggest more modeling.  Use JavaTC to estimate inductances and coupling factor.  (Include primary lead length, as that is often significant in high-frequency coils.)  Then use analog simulation (AC frequency sweep) to see the two poles and how close they are together.  Then check actual operation to make sure it is at upper of the two frequencies.  (Pole frequencies can be calculated with math rather than simulated.  Simulation is easier and graphical results more intuitive to understand.)  There are several free simulators, on-line ones and downloadable programs.  My favorite is LTSpice.  Repeat JavaTC and simulation for different primary heights and different cap values.

BTW, I just made my first QCW coil.  Still experimenting with it.  Straight arcs appear to be as much art as science.  Smooth voltage ramp is certainly a requirement.  I read here that humidity and surrounding object placement affect arc straightness too.
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #54 on: June 05, 2023, 12:55:10 AM »
Quote
I'm suggesting a single 3k resistor rated for 2.5W or higher across C18.  (Or could be a bit lower and higher power, such as 2.5k rated for 3W or higher.)
3k is fine as long as you have a resistor capable of at least 2.5W, and the warm resistor doesn't cause thermal issues for any neighboring components.
Ordered some 3.6k 5W SMD resistors before reading this. That should do the trick with room to spare.

Quote
Certainly a possibility. I was wondering about that as soon as you mentioned running at 350kHz.
I will try adjusting this again to be more in the range of the coil. The coil oscillation SHOULD take over but incase it doesn't is it better to be slightly under the res frequency or above it?

Quote
All this experimenting with relatively low primary capacitance is getting you close to dual-resonant coils.  There are always two resonances, even in normal SSTC designs.  Lower resonance (called lower pole) is normally far below normal SSTC operating frequency of upper pole.  Reduced primary capacitance moves lower pole closer to upper.  Boosts primary current and therefore performance as you have seen.  However, also makes it possible to lock to either frequency. 
That makes a lot more sense now, thanks for the info.

Quote
Rather than continuing with semi-random experimentation, I'd suggest more modeling.  Use JavaTC to estimate inductances and coupling factor.  (Include primary lead length, as that is often significant in high-frequency coils.)  Then use analog simulation (AC frequency sweep) to see the two poles and how close they are together.  Then check actual operation to make sure it is at upper of the two frequencies.  (Pole frequencies can be calculated with math rather than simulated.  Simulation is easier and graphical results more intuitive to understand.)  There are several free simulators, on-line ones and downloadable programs.  My favorite is LTSpice.  Repeat JavaTC and simulation for different primary heights and different cap values.
I'll take some measurements and plug some stuff into JavaTC. I have LTspice and was working on building a half bridge in it but there is a bit of a learning curve with it.

I am going to go back to using 0.47uf since that resulted in a nice boost to the output while keeping me far enough away from ZCS conditions. Dual resonance is a bit out of the scope for this project. While I know there is additional output to gain I want to keep this as a SSTC and eventually wrap up the project. I might try a DRSSTC or QCW next which will be a big next step for me.

That should give me some additional time to get more familiar with LTSpice and other simulation software. I know you advocate a lot for learning/testing via simulation. 





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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #55 on: June 05, 2023, 01:38:02 AM »
Quote
I will try adjusting this again to be more in the range of the coil. The coil oscillation SHOULD take over but incase it doesn't is it better to be slightly under the res frequency or above it?
I normally recommend slightly under res frequency.  Usually slightly above is fine too.  In your case, risk of hitting second mode of secondary is higher.  That rarely occurs.  However, with primary above bottom of secondary (creating capacitance to middle of secondary), risk is higher.  Any if I'm not mixing up threads, your previously failure experience suggesting secondary second mode as a likely cause.  ("Modes" is to distinguish from "poles".  Modes are analogous to higher modes of a wind instrument with multiple half-cycles along tube.)

Quote
I'll take some measurements and plug some stuff into JavaTC. I have LTspice and was working on building a half bridge in it but there is a bit of a learning curve with it.
AC sweeps are in many ways easier than more common transient analysis.  Model just the TC coils (with coupling factor) and capacitors (top load for secondary, C18, C19, and C20 for primary.  Use a voltage source and series resistor to model half-bridge.

Quote
I am going to go back to using 0.47uf since that resulted in a nice boost to the output while keeping me far enough away from ZCS conditions. Dual resonance is a bit out of the scope for this project. While I know there is additional output to gain I want to keep this as a SSTC and eventually wrap up the project. I might try a DRSSTC or QCW next which will be a big next step for me.
Sounds like a wise decision.
David Knierim

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #56 on: August 20, 2023, 12:31:07 AM »
Quote
I'm not quite clear.  Is the semi-transparent red showing showing what could be added, or what is already there?  Semi-transparent red area on Vbus+ (top of C18 and C19) is definitely helpful.  Output to primary coil is less important.  That current is already sine-wave due to primary inductance.  What does matter more is the path from high-side emitter to low-side collector.  This part of the one primary output node is important.  Current rapidly swaps from one IGBT to the other through the portion of this trace connecting the two IGBTs.  Some of that trace could be widened, the portion across C20 and C19.

Hopefully I implemented your advice correctly. I do have a few questions though.

Quote
Output to primary coil is less important.  That current is already sine-wave due to primary inductance.

I kept the primary output connector on the edge of the board and used the extra space to widen the copper pour. I don't think the extra distance to edge of the board will be an issue.

Quote
What does matter more is the path from high-side emitter to low-side collector.

I brought the IGBTs closer together than previous versions and also widened the copper pour to lower inductance. I hope there is plenty of copper now to reduce the stray inductance as much as possible.



PCB is 80mmx80mm to match the mounting points on an 80mm PC fan for cooling. Heatsink is located under PCB to save precious board space.

A few questions:
  • Should the neutral plane overlap all power (red) planes? I have most areas mirrored but wasn't sure if it was best practice to have the whole area poured like a typical ground plane.
  • Is there a problem with having the output power planes physically close together? They are space by 0.6mm. I was not sure if that might introduce crosstalk or result in other signal issues.
  • How do the GDT traces look? Q1 are nice and short while Q2 are ran sort or parallel (if that helps) but are a bit longer. Pin 5 is routed via trace to Q2 Pin 3 instead of going through the neutral plane per your advice

Any other design tips or best practices I can implement before ordering these new boards?

Red = Front copper power plane
Blue = back side logic GND or AC neutral








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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #57 on: August 20, 2023, 02:45:20 AM »
Quote
Hopefully I implemented your advice correctly.
Overall the layout looks really good.

Quote
Should the neutral plane overlap all power (red) planes? I have most areas mirrored but wasn't sure if it was best practice to have the whole area poured like a typical ground plane.
I'd increase it a bit, up to the center of pins of Q1 and Q2 across the rest of the ECB.  Keep it higher as you have it now from Q2 emitter to the right, at least to the left edge of primary output connector.  (Likely would be fine to extend neutral plane up further under gate circuitry, but that does add unwanted capacitance to high-side gate.)

Quote
Is there a problem with having the output power planes physically close together? They are space by 0.6mm. I was not sure if that might introduce crosstalk or result in other signal issues.
Most signals are 170V peak, max of 120Vac.  0.6mm is fine for all these.  The one exception is the lower output node (center of C19 and C20).  Voltage can be higher depending on values of C19 and C20 and how close your operating frequency is to resonance of C19+C20 with primary inductance.  Might be wise to increase clearance around all edges of that one shape, perhaps to 1mm or 1.5mm total instead of only 0.6mm.

Quote
How do the GDT traces look? Q1 are nice and short while Q2 are ran sort or parallel (if that helps) but are a bit longer. Pin 5 is routed via trace to Q2 Pin 3 instead of going through the neutral plane per your advice
Looks great!  That bit of trace length difference should not cause any problems.

Quote
Any other design tips or best practices I can implement before ordering these new boards?
Looking great!  Just the above small suggestions.
David Knierim

Offline ZakW

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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #58 on: August 20, 2023, 05:03:12 AM »
You're awesome Dave, thank you!

I moved the neutral plane up to the midpoint of Q1/Q2 and added a bit more clearance to the center of C19 & C20 per your suggestion.

Going to do a final pass tomorrow and get the files sent off to have them manufactured.


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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #59 on: August 20, 2023, 06:10:51 AM »
Quote
You're awesome Dave, thank you!
You are certainly welcome!  Glad to be of use.

Quote
added a bit more clearance to the center of C19 & C20 per your suggestion.
That entire node (entire copper shape) could use 1-1.5mm clearance, including at the secondary output connector lower pin (both layers), around mounting hole, and gap to other copper shapes.  Probably OK at 0.6mm, but a bit more would be good.  If connector pads themselves are closer together, may not be worth the work of editing the connector part itself in layout tool.  Even 0.6mm will typically handle 500V fine for the limited total use time of hobby equipment.
« Last Edit: August 20, 2023, 06:13:39 AM by davekni »
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Re: Ramped SSTC - Power Supply Question + General Improvements
« Reply #59 on: August 20, 2023, 06:10:51 AM »

 


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post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 19, 2023, 03:48:23 PM
post Re: Measuring electric voltage in a Tesla coil
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 19, 2023, 03:33:06 PM
post What to drive this UY30 transformer?
[Transformer (Ferrite Core)]
FPS
September 19, 2023, 09:06:16 AM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
RoamingD
September 19, 2023, 07:53:34 AM
post Re: Measuring electric voltage in a Tesla coil
[Dual Resonant Solid State Tesla coils (DRSSTC)]
omrid13
September 19, 2023, 07:14:57 AM
post Re: Enamel on secondary breaking down?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
September 19, 2023, 06:29:00 AM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
September 19, 2023, 06:15:40 AM
post Re: My QCW DRSSTC, small questions.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
September 19, 2023, 05:56:13 AM
post Re: Measuring electric voltage in a Tesla coil
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 19, 2023, 05:05:57 AM
post Re: Migatronic FocusStick 161E Stick Welder Teardown
[Electronic Circuits]
orac
September 19, 2023, 04:52:30 AM
post Re: Part identification for a Esab Es300i renegade Machine
[Beginners]
orac
September 19, 2023, 04:48:02 AM
post Re: Enamel on secondary breaking down?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
orac
September 19, 2023, 04:29:14 AM
post Measuring electric voltage in a Tesla coil
[Dual Resonant Solid State Tesla coils (DRSSTC)]
omrid13
September 19, 2023, 01:14:00 AM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
NyaaX_X
September 19, 2023, 12:59:52 AM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 19, 2023, 12:45:37 AM
post Re: Interrupter pulling ct signal
[Solid State Tesla Coils (SSTC)]
ZakW
September 18, 2023, 11:16:41 PM
post Re: Interrupter pulling ct signal
[Solid State Tesla Coils (SSTC)]
Egg
September 18, 2023, 09:55:08 PM
post Re: My QCW DRSSTC, small questions.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Lucasww
September 18, 2023, 08:15:37 PM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
Recep talip
September 18, 2023, 07:47:21 PM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
RoamingD
September 18, 2023, 07:46:46 PM
post Re: My QCW DRSSTC, small questions.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
All Science
September 18, 2023, 07:39:16 PM
post Re: Profdc9 Ud2.7C jumper question
[Dual Resonant Solid State Tesla coils (DRSSTC)]
dexter
September 18, 2023, 06:37:35 PM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 18, 2023, 06:20:30 PM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
RoamingD
September 18, 2023, 05:01:22 PM
post Re: Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
flyingperson23
September 18, 2023, 04:29:15 PM
post Drsstc feedback startup
[Dual Resonant Solid State Tesla coils (DRSSTC)]
RoamingD
September 18, 2023, 02:59:10 PM
post Re: My QCW DRSSTC, small questions.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Lucasww
September 18, 2023, 10:07:22 AM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
davekni
September 18, 2023, 06:07:25 AM
post Re: Anyone around with good coding skills (for the Flipper Zero)
[Dual Resonant Solid State Tesla coils (DRSSTC)]
ako
September 17, 2023, 09:46:42 PM
post Anyone around with good coding skills (for the Flipper Zero)
[Dual Resonant Solid State Tesla coils (DRSSTC)]
ako
September 17, 2023, 09:42:52 PM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
NyaaX_X
September 17, 2023, 06:05:59 PM
post Re: What Cable Thickness for Capacitor Discharges?
[Capacitor Banks]
MRMILSTAR
September 17, 2023, 04:48:28 PM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
Recep talip
September 17, 2023, 11:24:49 AM
post Re: What Cable Thickness for Capacitor Discharges?
[Capacitor Banks]
klugesmith
September 17, 2023, 07:00:02 AM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
davekni
September 17, 2023, 05:29:59 AM
post Re: Odd MOSFET Driver Behavior
[Solid State Tesla Coils (SSTC)]
davekni
September 17, 2023, 05:19:47 AM
post Re: My QCW DRSSTC, small questions.
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
September 17, 2023, 05:13:58 AM
post Re: First sstc is not working
[Solid State Tesla Coils (SSTC)]
Recep talip
September 16, 2023, 09:28:50 PM
post Re: Odd MOSFET Driver Behavior
[Solid State Tesla Coils (SSTC)]
KrisPringle
September 16, 2023, 04:33:30 PM

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