ZCS for SSTC without E class??

[AstRii]

Presumed the 1nF snubbers you mentioned were on each FET, so 2nF total.  Looking at FET data sheet for 0-90Vds, average capacitance was ~250pF each, 500pF total.  So ~2.5nF on bridge output, swinging 90V, for 2.5 * 90 = 225nC charge.  Presuming a bit more stray capacitance from GDT and bridge etc, I rounded to 240nC.  240nC / 4A = 60ns.

Thank you, that's very straight forward

That's typical behavior.  Arc loading increases as voltage increases, which reduces resonant Q.  Series-resonant impedance increases as Q drops.

That's very interesting, I would not have guessed that the impedance increases so quickly.

Unfortunately, my transistors have gave up today when running CW mode at 1.1kW.
I've redesigned the primary coil as it was heating up quite rapidly and used 2 primaries in parallel with the same wire guage. This lead to longer primary windings and thus higher coupling and higher power.
Due to this change I was able to get very nice output for a half bridge SSTC:

Unfortunately after 1minute and 28seconds running at full power in CW mode (230V, 1450VA, 1100W) the transistors blew up.

However, I think this was caused by my over temperature protection circuit. When this happened, the heatsink was about 60C, which means the transistors were most likely not much hotter than that (80C perhaps?). Not a sufficient temperature to kill the transistor. Nonetheless around 60C is the temperature threshold at which the over temperature protection circuit trips.



This is the circuit I've been using. I've specially placed a D flip flop so that the over temperature and UVLO only trips during "zero crossing". However I'm not really sure how that worked out.
I've been able to capture what happens on the bridge during UVLO trip from previous lower power tests:



(Red = primary current, Yellow = Drain-Source of low-side FET)
The ringdown looks pretty much as what I'd expect, however the primary current suddenly floating on what appears to be another sinewave looks odd to me.

Both transistors were completely destroyed (short between G-S, short between D-S). No other parts were damaged.
There isn't any visible damage on the transistors so it's hard to say which failed first.

What are your thoughts on this and on the overtemperature/UVLO circuit?

Thanks for any replies!

[davekni]

The ringdown looks pretty much as what I'd expect, however the primary current suddenly floating on what appears to be another sinewave looks odd to me.

What are your thoughts on this and on the overtemperature/UVLO circuit?

Simulate your gating and gate drive (including GDT).  You will learn more than if I try to explain.  Then compare with UD2.X.

When this happened, the heatsink was about 60C, which means the transistors were most likely not much hotter than that (80C perhaps?).

May be circuitry as you expect.  However, die inside IGBT packages are likely hotter than 80C.  Depends on power dissipation and thermal resistance inside package and package-to-heatsink.

[AstRii]

Simulate your gating and gate drive (including GDT).  You will learn more than if I try to explain.

I find simulators very intimidating and frustrating as they rarely work for me. Either ICs are not doing what they should or the simulation breaks due to some random 100MV spike or there are some transients which make it impossible to extrapolate anything valuable.


All of this is very demotivating for me, I prefer to learn fast, that's why I'm using this forum in the first place.

However, die inside IGBT packages are likely hotter than 80C.  Depends on power dissipation and thermal resistance inside package and package-to-heatsink.

Yes, unfortunately I do not have datasheet of the heatsink or thermal pads I'm using. I can only assume the thermal resistance between the transistor pad and the heatsink is not that high, as when I've touched the transistor case and the heatsink, they felt about the same. I think I can be confident about saying that the transistors did not reach 150C to break by overheating.

Then compare with UD2.X.

From my understanding, the circuitry is the same, a D flip flop and an AND gate. However I still think my accident was caused by my UVLO/over-temperature circuitry so something I don't understand must be different.

[davekni]

I find simulators very intimidating and frustrating as they rarely work for me. Either ICs are not doing what they should or the simulation breaks due to some random 100MV spike or there are some transients which make it impossible to extrapolate anything valuable.

Yes, simulating can be frustrating.  If you plan to work in analog electronics, simulating will likely be a necessary skill.  You'll learn techniques to minimize issues.  A few key ones below:
1) Use many initial condition statements (.ic statements).  Define reasonable voltages for key nodes.  Define initial inductor currents, especially if initial voltages would cause inductor current.  Usually setting inductor currents to 0 works well.  Sometimes non-zero current is good for rapid starting of oscillators.
2) Use as simple device models as will suffice.  LTSpice provides a couple basic opamp models for example, or use a voltage controlled voltage source.  If opamp bandwidth, drive current, etc. aren't critical to circuit, use simple models.  Use built-in LVDMOS model rather than fancier models from manufacturers.  BTW, I simulate with LVDMOS FETs even if actual circuit is IGBT.  I find IGBT models are often problematic.
2a) If details are critical for one or two devices, use manufacturer models for just those devices.
3) If simulation has issues after beginning, sometimes setting smaller time step helps.  Does slow down simulation, however.  Automatic dynamic time steps are usually fine.
4) Label all nodes (wires), or at least all that are being probed.  Makes read/communicating simulation results clearer.
5) Add some realistic parasitic series and parallel resistance to inductors.  Ideal (undamped) inductors sometimes cause issues.

Your posted simulation looks reasonable, though node labels and .ic statements will help.  I can't tell what nodes are being probed (nodes 4 and 7) without labels.  Probed voltage looks odd for any pair of nodes I can think of.  Also, add a defined number of pulses so pulses train ends to simulate end of enable time.  That enable end is the issue you want to study if I understand above post.  Also, I'd add GDT input parallel snubbing to make sure GDT primary matches real circuit.

[AstRii]

Yes I've spent whole night on it, but I think I understand why the accident happens.

During the overtemperature event, the driver basically keeps the Gates floating, meaning one of the transistors will turn off slowly (through secondary GDT winding).
If the transistor don't switch off quick enough (before the primary current starts another cycle), the transistor will suffer heavy loss and will fail.

I've solved this problem by using another winding on the GDT, that shorts the transformer to GND, eliminating any residual charge on the transistors.



I'm not sure how this will work in practice and I still can't wrap my head around why an UD2.7C driver does not need such feature, to me the GDT drive circuit looks the same.

[davekni]

I'm not sure how this will work in practice and I still can't wrap my head around why an UD2.7C driver does not need such feature, to me the GDT drive circuit looks the same.

They are not the same.  The difference is why you are having issues.  There can be a small residual GDT signal after UD2.7 disable.  There are posts on the forum showing GDT traces at the end of enable.  Generally residual gate voltage is below IGBT threshold.  Your clamp would help clean that up.  However, it is a klude to fix a basic gating issue with a clamp.

[AstRii]

They are not the same.  The difference is why you are having issues.

I think I understand the issue now. The difference is that my current driver after the falling edge of enable will have one gate driver outputting high and other gate driver outputting low. This means there will be full input voltage across the GDT primary (not causing a short circuit thanks to the DC blocking capacitor). This also means that the secondaries of GDT will have nowhere to discharge.

However UD2.7 gate drivers will both output the same logic state (high) after the falling edge of enable.
This shorts GDT secondaries through the gate driver's high side PMOS through the voltage source it's being powered from to GND. Removing any charge from the Gates of power transistors.

Did I get that right?

Unfortunately I was in a rush to order new PCB as this coil needs to be finished soon. So the new driver PCB will use the "clamp" winding.


I will use UD2.7 output stage in the next iteration or perhaps even galvanically insulated Gate driver ICs. 

[davekni]

I think I understand the issue now. The difference is that my current driver after the falling edge of enable will have one gate driver outputting high and other gate driver outputting low. This means there will be full input voltage across the GDT primary (not causing a short circuit thanks to the DC blocking capacitor). This also means that the secondaries of GDT will have nowhere to discharge.

However UD2.7 gate drivers will both output the same logic state (high) after the falling edge of enable.
This shorts GDT secondaries through the gate driver's high side PMOS through the voltage source it's being powered from to GND. Removing any charge from the Gates of power transistors.

Did I get that right?

Yes, with one tiny change.  UD2.7 gate drivers output high, so low side NMOS FETs are on.  Otherwise exactly correct.

Unfortunately I was in a rush to order new PCB as this coil needs to be finished soon. So the new driver PCB will use the "clamp" winding.

Clamp solution does leave one issue unresolved:  The DC blocking capacitor starts charged rather than at 0V.  Given lower IGBT current at start of enable, this start condition issue MIGHT not cause failures.

At the risk of providing too much information:  Your boards are trivial to patch.  Just use the driver chip enable pins instead of AND gate on input.  UD2.7 avoids using enable because that would leave driver chip outputs low.  Low driver outputs would turn on PMOS outputs, except that PMOS gate drive is AC-coupled.

[AstRii]

Yes, with one tiny change.  UD2.7 gate drivers output high, so low side NMOS FETs are on.  Otherwise exactly correct.

Thanks a lot for the confirmation

The DC blocking capacitor starts charged rather than at 0V.

Wouldn't a discharging resistor parallel to the cap solve this issue?

Just use the driver chip enable pins instead of AND gate on input.

I have thought of that, however IXDN6XX / IXDI6XX drivers do not use the enable pin. There is a IXDD6XX version of the non inverting driver that uses it, however there is no such option for the inverting chip. Also the IXDD6XX chip outputs High-Z instead of low when enable is low, that is not much helpful. I've picked these drivers a long time ago since they are in a TO220 package so they are easy to cool and they are not much costly, however now I see they are not the best in this situation.

[davekni]

Wouldn't a discharging resistor parallel to the cap solve this issue?

A resistor might help a little with how fast cap discharges after enable starts.  Doesn't fix issue.  Mostly wastes power and starts GDT primary with some DC current.

I have thought of that, however IXDN6XX / IXDI6XX drivers do not use the enable pin. There is a IXDD6XX version of the non inverting driver that uses it, however there is no such option for the inverting chip. Also the IXDD6XX chip outputs High-Z instead of low when enable is low, that is not much helpful. I've picked these drivers a long time ago since they are in a TO220 package so they are easy to cool and they are not much costly, however now I see they are not the best in this situation.

OK, makes sense.  I'd looked at your schematic symbol and not at part data sheet.  Unusual to have high-Z as the disabled state.  If the chip version you were using had enable, high-Z combined with your clamp and some resistance across DC coupling cap would fix everything.

[AstRii]

Actually what I forgot to mention is that I also changed the IXDN609 for IXDD609 and routed the Enable pulse to its enable pin. It's funny because I did this change without simulating it or thinking about it, as I said I was in quite a hurry to order new PCB and I had just an intuition that this change will help.

If the chip version you were using had enable, high-Z combined with your clamp and some resistance across DC coupling cap would fix everything.

I'm so glad to hear this confirmation. Thanks a lot. I will keep you updated when the new PCB arrives