loneoceans driver board

[Garyf]

Are there users of the loneoceans 2.7 driver board who have noticed this?

I assembled the board, put signals to the interrupter and feedback inputs, and scoped the GDT outputs.  One of them has a partial 140 ns pulse before it's cutoff by the flip flop output.  Phase lead and c33 don't have any effect.


Not an easy way to fix it on an SMT board. 
1. Has anyone built this board and noticed this?
2. Is it not a problem because it's too fast for the IGBT to respond?  My history with ZCS problems makes me want a clean signal.

Loading the FF output with 100 ohms to ground reduced the switching time and made the glitch disappear, but I don't think this is a good solution.

[Mads Barnkob]

I have not build loneoceans UD2.7, but I will say that this behaviour is from the original UD design, as I have seen similar spikes at the end of a pulse train in those drivers.

However, at 140ns and such a small magnitude, I would not worry about it, if we are talking brick IGBTs there is hardly any energy there to change the state of the gate charge. I do not think it is a problem, but as you could remove it with a resistor on the FF ouput, that must indicate that it is a even shorter glitch first initiating it, since it dies out completely? ungrounded unused pins on some ICs? Internal crosstalking in ICs?

[Hydron]

I think I have seen this too, and it did cause spikes at the end of the burst as I was using fast TO-247 parts with low gate charge rather than bricks.

I was just using the driver for low voltage testing so didn't worry about it at the time, but it certainly isn't ideal!

[Mads Barnkob]

I did actually have some saved oscilloscope screenshots of this little pecker, back from 2013 where I only had a Rigol DS1052e. These are from my DRSSTC3 which uses UD2.1b

[Scott Fusare]

I have seen this on both UD2.1, as well as UD2.7 drivers that I have built.

I once queried Steve Ward about it and he commented this glitch has always been present in the UD2.x drivers. Given its brevity the transformer should pass little, if any of it.

Scott 

[Garyf]

Thanks all for weighing in!  After much poking and probing, I find that it goes away with a 47pf cap to ground on the output of the NAND gate.  Mads was right that it's very narrow at the origin. 
I found that a 6pf cap on the other NAND gate output makes the switching times match well.
This may be unnecessary but I have a large bag of dead TO-247s: not all the failures were understood.

[futurist]

I never noticed this on my UD2.7, are there any special conditions needed to replicate this glitch?

[Garyf]

Nothing special. My simulated feedback signal was about 100khz and I had GDT loading on the output.  The interrupter signal takes two paths to the AND gates, IC5A and B. One path is direct and the other is thru the FF.  I notice the tolerance on propagation delay thru the FF is 17 to 44 ns.....?

[futurist]

The interrupter signal takes two paths to the AND gates, IC5A and B. One path is direct and the other is thru the FF.

How do you mean one path is direct and the other is trough flip-flop?

[Hydron]

When pin 7 of the TL3116 (IC8 in the schematic here: http://www.loneoceans.com/labs/ud27/UD27Cschematic.png ) is going high, it both drives one pin of the IC5B AND gate, and also clocks in the interrupter enabled/disabled state into the IC6B flip-flop.

If the interrupter has been disabled within the last period, this causes the Q output of IC6B to go low and force both AND gate outputs low.

The key here is that IC5B is driven by the direct signal from TL3116, and also the indirect signal from the flip-flop, which will have a small added propagation delay. This delay causes a small period where both AND gate inputs are high (and thus the output is high), before the signal from the flip-flop changes and forces the output low. The other AND gate (IC5A) does not have this issue as it's output is already low when the interrupter disable event occurs - the change in state of the flip-flop does not affect it's output.

[Garyf]

Good explanation! A future driver revision might consider using the unused gate IC5D as a buffer to match the delays.

[Hydron]

In my opinion, using something like Philip's UD+ design would be a better way to go than continuing on the UD2.x path. It has the downside of needing to program (or obtain a pre-programmed) CPLD, but is otherwise more flexible and doesn't suffer this sort of issue.

However, if someone does want to make a new revision of the UD2.x driver then it's certainly worth looking into eliminating the problem, though it's probably more difficult than just using IC5D (which will not have the same delay as the flip-flop causing the issue).

[futurist]

Hydron thanks for the explanation

I was playing with my UD2.7 this morning and I couldn't replicate the problem
Propagation delay through flip-flop is 20-40 ns, same like on Garyf's driver

Here are scope shots of IC5B





Pin 4 - yellow
Pin 5 - blue

[Garyf]

Best place to see it is compare IC5A and B outputs at the phase jumpers.

[Tardief]

Hi

I have a question about Loneocean's controller, but could find the proper topic.

We have a DRSSTC with Lonecocean's ud2.7C and with his MIDI Controller.
The controller has a maximum frequency of 300Hz in fixed mode. (Similar to the Easter Voltage interruptor) Why is this?
Is it because of the duty cycle? With a 200us max pulse width and 300Hz it would be 60ms on time in 1 sec, that's 6% Duty cycle.
A MIDI file contains notes with much higher frequencies. Like the A4 note is 440Hz, a C6 is 1046. How is it still good?