Mystery MOSFET faliure

[Lucasww]

Hello all, I've recently been working on a small desktop SSTC based on the circuit from here:
http://skory.gylcomp.hu/tesla/mini_tesla.html
http://skory.gylcomp.hu/tesla/mini_tesla2.html

schematic of my version is attatched. (I am using RX3R05BBHC16 150V 50A MOSFETs, not the ones in the schematic. D1 & D2 are 13V bidirectional TVS Diodes.)

It works great, I'm able to get sparks over 3 inches from a 2 inch secondary at 24v, however I keep killing MOSFETs and I can't figure out why.
I killed 5 of them trying to figure it out, but here's what I know so far:
- Only Q1 fails. I have never killed Q2. Don't know why.
- The MOSFET fails with all 3 pins dead short.
- Drain voltage is almost certainly not the issue, I've been monitoring it with a scope and it never goes above 80v as far as I can tell.
- the MOSFETs aren't heating up significantly. I even ran it without a heatsink, barely any noticeable heating until Q1 fails.
- Gate voltage looks fine, I have tvs diodes across them and haven't seen any concerning voltage spikes.
- It has failed with input voltage as low as 17V
- It usually seems to fail with the BPS set higher, above maybe 20BPS. This may just be because it has to start and stop more often, and it seems likely that the issues happen at startup
- I haven't been able to get it to fail with the jumper J1 open, although the output is also significantly smaller with it open. (the parallel LC network adjusts the feedback phase). I replaced L2 with 47uH, thinking that 22u was maybe too little, but it didn't seem to fix it.

I have 2 videos watching the drain and gate voltage as it failed, and the only interesting thing i noticed is, in one of them (but not the other), the gate voltage suddenly started rising up to the threshold voltage much faster than normal right before it failed. It normally takes a few dozen microseconds for the gate voltage to rise up to its threshold and start oscillating.

Other than that, I have absolutely no clue what is going wrong. I have used this circuit in the past with no issues. Any ideas are appreciated.

[davekni]

D1 & D2 are 13V bidirectional TVS Diodes

That may be part of the problem.  As GDT output voltage increases towards 26Vpp, average gate voltage will drop to 0.  There will be some dead time when neither FET is conducting.  Primary leakage inductance will cause a voltage spike when both FETs are off.  Looks like good snubbing to catch that in the circuit diagram.  However, layout is critical for snubbing to work well.  Perhaps add fast (schottky or signal) diodes from gates to ground to clamp negative gate voltage.  Perhaps resistors or zener diodes in series with diodes to allow a bit of negative Vgs.

It usually seems to fail with the BPS set higher, above maybe 20BPS.

Is C12 really 22nF?  Unless I'm analyzing the circuit wrong, values shown would not allow BPS below 500/second or so.

Only Q1 fails. I have never killed Q2. Don't know why.

Circuit is almost symmetric.  Suggests that layout or wiring parasitics are causing Q1 to fail first.  Q2 may be stressed some, but not quite as much.  Only asymmetry that I notice would be winding capacitance from GDT primary to secondary.  An image of GDT might help just in case that is relevant.

I have 2 videos watching the drain and gate voltage as it failed, and the only interesting thing i noticed is, in one of them (but not the other), the gate voltage suddenly started rising up to the threshold voltage much faster than normal right before it failed.

Nice work capturing the failure on scope!  That can be quite difficult.  I'm presuming Q1 Vgs is the one rising faster.  My guess is that Q1 has already partially failed at that point.  Leakage current from gate to drain is pulling gate high faster.  Leakage current then progresses to a full short.

How long on-time are you running for your 20BPS failures?  What is the supply current?  What frequency is the coil oscillating at, both with and without J1?  What is primary inductance? (An estimate from JavaTC would be fine.  Even better would be both primary and secondary values from JavaTC.)  Picture of ECB and scope captures of normal pre-failure operation would probably be useful too (ie. at low BPS to avoid failure).

[Lucasww]

That may be part of the problem.  As GDT output voltage increases towards 26Vpp, average gate voltage will drop to 0.  There will be some dead time when neither FET is conducting.  Primary leakage inductance will cause a voltage spike when both FETs are off.  Looks like good snubbing to catch that in the circuit diagram.  However, layout is critical for snubbing to work well.  Perhaps add fast (schottky or signal) diodes from gates to ground to clamp negative gate voltage.  Perhaps resistors or zener diodes in series with diodes to allow a bit of negative Vgs.

I will look into this. I believe my layout is pretty decent.
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(idk why these attachments don't embed, but you can see them at the bottom still)

Is C12 really 22nF?  Unless I'm analyzing the circuit wrong, values shown would not allow BPS below 500/second or so.

SW is a 1p6t switch that adds another capacitor in parallel with C12, allowing me to vary the BPS down to around 1.

An image of GDT might help just in case that is relevant.

Primary is 18T magnet wire, secondary is 9T
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(also attached at the bottom)

How long on-time are you running for your 20BPS failures?  What is the supply current?  What frequency is the coil oscillating at, both with and without J1?  What is primary inductance? (An estimate from JavaTC would be fine.  Even better would be both primary and secondary values from JavaTC.)  Picture of ECB and scope captures of normal pre-failure operation would probably be useful too (ie. at low BPS to avoid failure).

I have had it fail with the ontime lower than 100uS, short enough that no sparks even form. I wasn't measuring supply current but I can't imagine it was very high. Coil is oscillating at ~1MHz with J1 closed, ~900kHz with it open. Primary is center tapped, one turn on each side with very tight coupling between halves.


here's some scope shots at 16V input. Top is D-S, bottom is G-S


I noticed a weird spike in the gate waveform at startup (20V input). I don't know if this is real or just interference (the probes are very close to the coil), but it's interesting nonetheless.

[davekni]

I will look into this. I believe my layout is pretty decent.

Yes, your layout looks great.  Nice ground and power planes.

Primary is 18T magnet wire, secondary is 9T

Looks well made.  Capacitance between winding still makes a bit of asymmetry between Q1 and Q2.  May help to have some scope captures showing Vgs of each FET and another showing Vds of each FET.

here's some scope shots at 16V input. Top is D-S, bottom is G-S

Thank you for the scope captures.  Provides much better background for for your coil.
First scope capture shows longer Vds low time than high time suggesting voltage is lagging current.  That phasing likely changes with L2 value and with operating conditions (arc length etc.).  Third capture looks like voltage is leading current a bit.

I noticed a weird spike in the gate waveform at startup (20V input). I don't know if this is real or just interference (the probes are very close to the coil), but it's interesting nonetheless.

I'm guessing that is real, though I'm struggling to explain its timing slightly after Vds rise rather than simultaneous.  Even with your good layout, fast transitions into high gate capacitance make trace and part lead inductance significant.  This condition of voltage phase leading current (3rd capture) may warrant further exploration.

Another possibility is that FET current ramps too high before oscillation starts.  Measuring current is difficult.  Perhaps some hint of current can be detected by voltage drop across bypass caps on V+.  Perhaps a scope capture of V+ with scope input in AC-coupled mode and at 1V/div or under would show useful information on initial voltage droop.  (One of the rare cases where AC-coupled mode is useful.)

[Lucasww]

Nice work capturing the failure on scope!  That can be quite difficult.  I'm presuming Q1 Vgs is the one rising faster.  My guess is that Q1 has already partially failed at that point.  Leakage current from gate to drain is pulling gate high faster.  Leakage current then progresses to a full short.

missed this part of your first message. That was what I was thinking as well, I don't know anything else that would cause it. It seems plausible.

I decided to look into the gate voltage spike more, It seems to be something that happens somewhat consistently on startup. That would explain why it fails with high BPS and low on-time but not low BPS and high on-time, if startup is the only problematic part.



(yellow D-S, green G-S)
here's how the gate is being probed.


What I'm confused about is why the TVS diodes aren't clamping that at all? They are SMAJ13CA diodes. also no idea where the spikes are coming from.

[davekni]

(yellow D-S, green G-S)
here's how the gate is being probed.

Probing looks great!  Are the two probe coax leads back to scope very different in length?  Or perhaps is the scope set for different delays on the two input channels?  Looks like ~30ns delay difference.  Perhaps worth connecting both probes to the same signal to see if delays match.

What I'm confused about is why the TVS diodes aren't clamping that at all? They are SMAJ13CA diodes. also no idea where the spikes are coming from.

Fast rise of Vds generates a current spike into gate.  Spike is some combination of interconnect and device lead inductance and TVS diode forward recovery time.  Even though interconnect is quite short, the spike is also short.  There will be significant drop across even the short traces from FET to TVS diode.  You could scope across diode package to get some idea of this contribution.  (Spike at FET die inside package will be even a bit higher than what your scope shows due to FET lead inductance.)  Other contribution is internal TVS diode forward recovery time.  Bidirectional TVS diodes are internally two unidirectional diodes series connected back-to-back.  It is possible to get faster response using unidirectional TVS diodes and schottky diodes.

[Lucasww]

Probes are the same length and delay is the same. connecting them to the same spot shows the same signal.

I tried probing around and I found something interesting, it seems like the spikes are coming from the LC feedback circuit. With J1 open, that part is left out of the circuit and there is no spikes on the gates, with it closed the spikes come back. Probing between R4 (the side not connected to the GDT) and ground shows this:
(J1 open)

(J1 closed)


Not sure what would cause the spikes, it should just be acting more or less like a resonant circuit. Running the circuit with J1 open, It seems completely stable but the output is maybe 70% as big. I've seen some chinese implementations of a similar circuit (the ZVS version of this circuit, basically), which use a capacitor in series with the GDT instead of the parallel LC. maybe this is a known issue.

[davekni]

Probes are the same length and delay is the same. connecting them to the same spot shows the same signal.

Did you check with horizontal expanded enough (50ns/div or under) to see a 30ns delay difference?

I tried probing around and I found something interesting, it seems like the spikes are coming from the LC feedback circuit.

I'd phrase this a bit differently.  LC feedback circuit changes result in a relative change of primary current and primary voltage.  That phase change affects Vds voltage rise.  When Vds rises rapidly, Cdg couples to gate, generating the spike.

[Lucasww]

Did you check with horizontal expanded enough (50ns/div or under) to see a 30ns delay difference?

I believe I did, although I can try again later.

Are you sure Cdg has to be the cause of the voltage spikes? It seems strange that they don’t line up and the spikes are entirely gone when not using the LC feedback circuit.

[davekni]

I believe I did, although I can try again later.

Perhaps test with scope settings exactly the same as your Vds/Vgs measurements, even though different vertical scales will make alignment check slightly more difficult to view.  Just to rule out any possible scope artifact such as delay depending on vertical gain setting.  50ns/div was the setting for the obvious 30ns difference in Vds to Vgs.  I'd test at that horizontal scale too.  Everything exactly the same.

Are you sure Cdg has to be the cause of the voltage spikes? It seems strange that they don’t line up and the spikes are entirely gone when not using the LC feedback circuit.

No, I am not certain.  That's why the question about alignment.  Looks exactly like Cdg except for alignment.  And I cannot think of any other possible cause.

Perhaps someone else has other ideas for causes.

[Lucasww]

Perhaps test with scope settings exactly the same as your Vds/Vgs measurements, even though different vertical scales will make alignment check slightly more difficult to view.  Just to rule out any possible scope artifact such as delay depending on vertical gain setting.  50ns/div was the setting for the obvious 30ns difference in Vds to Vgs.  I'd test at that horizontal scale too.  Everything exactly the same.

Tried this, there was no noticeable difference in delay. I'm not sure where to go from here.

[davekni]

Tried this, there was no noticeable difference in delay. I'm not sure where to go from here.

I'm out of ideas.  Hopefully someone else can contribute.

Perhaps scope other FET Vgs (instead of this FET's Vds) during a glitch.  And perhaps GDT primary along with this Vgs glitch.  Might provide some clue.

[NyaaX_X]

When I was testing my secondary feedback single MOSFET Class-E style SSTC from Steve ward website and teslaundmehr. I sometimes meet the MOSFET broken issue. They happen seems like your case.
When I turn on the power. The MOSFET dead right away. No spark, no sound, no heating. Three of the pins shorted.I was thinking and guessing that is because the spark of coil did not grow up so the loaded let the Class E amplifier far away from correct tuning and the Vds jump over the limit so break MOSFET rapidly.

That is my guessing. Now I still do not sure why my circuit dead. But if I what to make a Class E SSTC I tend to make a fixed-frequency CW one and use low power to spark the arc manually. Then push up the power. I think the pulse working one have more risk that breakdown the MOSFET before it run stably. So sadly I don't have more imformation of it.

But here I suggest you try to remove the topload and let the discharge pin more easily to shoot out sparks. Maybe it can improve it or not.. If that plays better then you can add the topload and make a longer pin that have a suitable breakout point and charging shape.

https://www.stevehv.4hv.org/classEsstc.htm
https://youtu.be/wnPZmrfY2MY?feature=shared