IGBTs refuse to cooperate

[Jesperb123]

Hi!
It's been a while since I last posted here but I've been working hard on my drsstc whenever possible (during summer breaks due uni-studies).
Unfortunately I've managed to get stuck and need some guidance on how to get past this roadblock. A pre-emptive apology is in place; this will be a long post.

Some basic system specs:
Driver: ud 1.3b with my own PCB (w. IC-sockets and test points):


Primary LC-circuit:
C1 = 0.2uF, L1 = 1.018uH => Fres = 353kHz
Secondary LC circuit:
C2 = 8.426pF, L2 = 24.2mH => Fres = 352kHz
(Capacitive/inductive reactance at 352kHz is 53,5kOhm)
H-bridge with IGBTs and w. TVS/zener diodes:
IKWH60N65WR6 (650Vce max)
Two 1.5KE220CA (bidirectional) TVS diodes in series across collector and emitter of each IGBT.
A 30V zener diode (P6KE30CA) across the gate and emitter of each IGBT.
Other notes:
Oversized 4700uF, 450Vdc cap + full bridge rectifier
I'm using a cascaded CT/FT setup with 14 turns on the secondaries on both cores (1 turn on the primaries). The secondary side and enclosure/heatsink is
grounded according to the scheme Mads made a while back.

The system was designed for 200A but I'm given the difficulties i'm having I would not put any faith in that number
Pictures of the system:


Equipment note: I have a variac, multimeter, oscilloscope, labsupply and a function generator at hand. I don't have access to differential probes or a proper current transformer.
I built a coilwinding machine which uses a steppermotor (I can set speed, direction and it counts the number of turns made):


I've tested the system a total of 4 times and during the latter 3 i've managed to kill both transistors in the right leg of my H-bridge (all 3 terminals have failed short).
I believe the driver works properly because it behaves as expected. To make things easier to follow/analyze i'll describe the four tests below:

Test 1 (at uni)
Here I used a helical primary and got racing sparks at a low bus voltage (see the attatched video). No IGBT failure occured during this test.
I checked the output of the GDT (without the bridge connected) by connecting the ends of 4 secondaries together (to serve as the reference)
and probed the remaining four wires with a oscilloscope like so:

(I also wanted to ask if this is a valid way of measuring the GDT output?)

The actual gate-voltage when connected to the tranistors was never checked. Here's a video of test that's hosted on my google drive:
https://drive.google.com/file/d/1FNJ4yWYNc4_DziCNGYRGblhohgXMWfLD/view?usp=sharing
I realized (after test 3) that the MMC capacitance was 0.68uF during this test (supposed to be 0.2uF) and that the gate-drive voltage during this test was horrible due
to the diode I used in parrallel to the gate resistance:


Test 2
I replaced the helical primary with a pancake primary to reduce coupling (thinking that this would solve my problems with racing sparks) and made a new secondary L.
I was still using the diode in parallel with the gate resistance during this test. The right leg of the H-bridge failed at around 90Vdc and I later found out
(when troubleshooting the system for test 4) that one string in my MMC had failed open so I was in inadvertently using the MMC at 0.45uF. I had flourescent tubes
placed in the background which lit up slightly during this test.

Test 3
I rebult the H-brige by replacing the failed IGBT's and kept the ones that had not failed short. Here I was still unaware of the MMC issue so I ran the system again,
and the bridge failed at around 90Vdc in the exact same manner (IGBT's in right leg failed; all three terminals of failed short).

Test 4
Here I figured that something more fundamental must be wrong so I did my best to find faults in the circuit before test 4. Since i'm using the Ud 1.3 driver
I was supplying the GDT with +- 24V, and due to ringing I managed to get peaks of +-32V. The waveforms in the picture is the output from the GDT measured
using the technique presented above. The secondaries were not connected to the bridge.



I replaced the 24V regulator with a 15V regulator and the waveform now has peaks at +-20V. I've read on Mads page that most IGBT's can handle more than the absoulte
max rated Vge mentioned in the datasheet (which is good since they'll turn on more) but I didn't feel like leaving this to chance once more. I also removed the diode from
gates of the IGBTs and increased the gate resistance from 4.7ohm to 8.7ohm which cleaned up the waveform nicely (here I'm measuring the actual gate voltage):



I made the driver run (without driving a current through the primary LC-circuit) by disconnecting the feedback circuitry with a jumper and then "injected" a substitue signal connected as such:



As mentioned earlier I found the MMC error here and replaced the MMC with one that has the correct capacitance (0.218uF ~ 0.2uF). I replaced all TVS and zener diodes and all IGBT's to make
sure no undetected failures would affect this test. I then conducted the test and the IGBT's in the right leg failed once more but this time at 70Vdc.
Here's the video: https://drive.google.com/file/d/1BKFW3-gKo87UF1U_2Go0uTCz-5N2gWw4/view?usp=sharing

It's hard to see but there appears to be some very small discharges occuring at the breakout point. I believe I forgot to tape the secondary wire to the ground plane during this test but I don't think it
made much of a difference. Finally, here is close up pictures of the H-bridge just before test 4 (I trippled checked that all connections were right but i'd be delighted if you can find the issue : ) ):



Comments, ideas and plan of action
I only got two spare IGBTs and they keep failing in the same manner but I cannot figure out why. Additionally it takes a suprisingly long time to fix the H-brige so I'd like to make a low inductance PCB
(somewhat similar to loneoceans Easybridge) to make replacements easier - but I need to figure out why my IGBTs keep failing before.

I've also thought about probing the Vce of the IGBTs(with low-Vbus voltage) but I've been hesistant to do so since I might damage the scope? Here's a picture of how I'd do it and
the waveforms I believe I should expect:

(I've also noticed that connecting PE (oscilloscope earth) to Vbus ground trips the RCD when Vbus voltage is applied (so it might not be possible regardless)).

I've read about IGBT latchup and thought the earlier failures could've been due to this (maybe the gate got destroyed from overvoltage while IGBT was conducting and then shoot-through occured?). If my way of measuring the Gate voltages was ok I believe the phasing was correct so I don't think this was the issue. The heatsink felt fairly warm immediately after failure but not overly hot - I could press my fingers against it without them hurting too bad. I'm at a loss as to why this keeps happening (and why the right side keeps failing - especially when the gate voltages on the right sight looks similar to the ones supplied to the left side).

I'll buy differential probes if its absoulutely neccessary but any wise advice would be greatly appreciated.

Best regards,
Jesper

[flyingperson23]

I use my oscilloscope without a differential probe mostly successfully by isolating its ground (i.e. plugging it in with a 3 prong to 2 prong adapter)

This is a random guess, I have little experience with small igbts, but the datasheet indicates the turn off delay time is 10 times the turn on delay time. Is cross conduction a possible problem source?

[Rafft]

1st, why is there a diode in series of IGBT? what are you trying to do? bypass the internal diode? if so, then you would need(add another) faster diode anti-parallel to IGBT+series diode.

and maybe that is the reason why those IGBTs keep failing.

and maybe replace 1.3b with at least 2.7x. phase lead adjust helps in keeping currents lower

[davekni]

IKWH60N65WR6

This is a random guess, I have little experience with small igbts, but the datasheet indicates the turn off delay time is 10 times the turn on delay time. Is cross conduction a possible problem source?

It is difficult to translate data sheet times to typical DRSSTC use, especially since spec is for 0-15Vge rather than -15 to +15Vge.  However, I agree with flyingperson23 that cross conduction is likely one of several issues here.

353kHz is fast for IGBTs, especially without phase lead and with this relatively-slow IGBT (slow in Toff only).

I see no snubber caps (high frequency bypass caps) across Vbus at each half-bridge.  Likely the biggest single issue.

The heatsink felt fairly warm immediately after failure but not overly hot - I could press my fingers against it without them hurting too bad.

IGBT insulating pads make IGBT case temperature significantly higher than heatsink temperature.  For your short runs, I'm guessing IGBT power dissipation and temperature is rather high, caused by other issues here.

I use my oscilloscope without a differential probe mostly successfully by isolating its ground (i.e. plugging it in with a 3 prong to 2 prong adapter)

This works well, but two cautions:  Most important is safety.  Scope chassis including all probe ground clips are at line voltage.  Don't touch.  Second, connect probe ground to VBus-, not to one of the bridge outputs.  High frequency signals on scope "ground" will pass through scope's internal line Y caps and cause issues with measurement accuracy and/or coil operation.  For Vge phasing (GDT output phasing), scope with very low Vbus, 5V to 20V.  Then high-side gates can be probed with scope ground to Vbus-.  Bridge output will be superimposed on Vge, so takes a bit of thinking to interpret.  Good mental exercise.

I've also thought about probing the Vce of the IGBTs(with low-Vbus voltage) but I've been hesistant to do so since I might damage the scope?

Since you have a lab supply, use that for Vbus for low voltage testing.  If probes are selectable between 1x and 10x, tape or glue the switch to 10x.  There are few cases where you will need 1x.  At 10x, unlikely to damage scope.  Tape or glue prevents accidental switching to 1x and possible resulting scope damage.  Do verify probe voltage rating before use.

Here I used a helical primary and got racing sparks at a low bus voltage (see the attatched video). No IGBT failure occured during this test.

Secondary coil aspect ratio is rather high (tall compared to diameter).  That makes racing sparks more likely.  Reducing coupling fixes racing sparks.  However, low coupling hurts performance.  Try JavaTC to estimate coupling for your geometry.

The actual gate-voltage when connected to the tranistors was never checked.

Vge is important to check.  Shows if you have sufficient dead time and fast enough rise and fall times and reasonable over/undershoot.  Diodes across gate resistors are usually necessary for IGBTs.  Add some series resistance to diode if undershoot is too bad.  TVS diodes should clamp undershoot to a reasonable level.  If you want +-30V peak, you will need lower rated voltage TVS diodes for Vge, around 24V rating.  BTW, I like ~19V laptop supplies for gate drive.  Nice compromise between 15V and 24V.

Additionally it takes a suprisingly long time to fix the H-brige so I'd like to make a low inductance PCB

Yes, low inductance, especially to the snubber caps (that are missing now) is important.  Another option without making a "real" PCB is:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886

Two 1.5KE220CA (bidirectional) TVS diodes in series across collector and emitter of each IGBT.

Are these TVS diode(s) frying too?  For most designs it is better to not use Vce TVS diodes.  Most IGBTs have higher avalanche energy ratings than do the TVS diodes.  However, your parts have no avalanche energy rating.  So TVS diodes may be of value here.

Your GDT itself looks very well constructed.  Total leakage inductance can be reduced by keeping leads as short as feasible.  Your leads are nicely twisted together.  If all four primary winding leads are brought out as four twisted pairs and then paralleled at driver board, leakage inductance will be further reduced.  Minimizing leakage inductance allows reducing gate resistance for faster switching.

Good luck with your build!

[Jesperb123]

I use my oscilloscope without a differential probe mostly successfully by isolating its ground (i.e. plugging it in with a 3 prong to 2 prong adapter)

This is a random guess, I have little experience with small igbts, but the datasheet indicates the turn off delay time is 10 times the turn on delay time. Is cross conduction a possible problem source?

Yeah this seems plausible given the low voltages they keep failing at. I'm still perplexed as to why the IGBT's in the right leg always fail and not the ones in the left leg?

1st, why is there a diode in series of IGBT? what are you trying to do? bypass the internal diode? if so, then you would need(add another) faster diode anti-parallel to IGBT+series diode.

The two series diodes placed across the IGBTs are transient voltage suppressors meant to clamp any large transient Vce voltage to a safe level (less than the maximum Vce ratings of the IGBTs) in order to protect them. They're not meant to replace the internal diodes of the IGBTs. The ones I use have a reverse breakdown voltage of 185V (i.e they will appear as a high-impedance with voltages < 370V due to two being in series). They should begin clamping hard before 650V which ought to protect the IGBTs.

Here's a schematic from Steve Ward using TVS diodes:

Two 1.5KE220CA (bidirectional) TVS diodes in series across collector and emitter of each IGBT.

Are these TVS diode(s) frying too?  For most designs it is better to not use Vce TVS diodes.  Most IGBTs have higher avalanche energy ratings than do the TVS diodes.  However, your parts have no avalanche energy rating.  So TVS diodes may be of value here.

No they're all intact (i.e they haven't failed short) and I'd be suprised if that was the case given the low voltages I was using during all tests.

353kHz is fast for IGBTs, especially without phase lead and with this relatively-slow IGBT (slow in Toff only).

I see no snubber caps (high frequency bypass caps) across Vbus at each half-bridge.  Likely the biggest single issue.

I agree, but seeing as LoneOceans DRSSTC 1 had a fairly high resonant frequency (270kHz) and was similarly sized so I thought this wouldn't be an issue. I should have spent more time searching for a suitble IGBT I guess. Do you think it would be easier to find a suitable power Mosfet?

I'm not familiar with using snubber capacitors across Vbus at each half-bridge, I thought they were only used to reduce the power loss in the switching device (while dissappating this removed power in the snubber resistor). What's the reason for this use case? How does one select the proper capacitance?

IGBT insulating pads make IGBT case temperature significantly higher than heatsink temperature.  For your short runs, I'm guessing IGBT power dissipation and temperature is rather high, caused by other issues here.

Noted.

Here I used a helical primary and got racing sparks at a low bus voltage (see the attatched video). No IGBT failure occured during this test.

Secondary coil aspect ratio is rather high (tall compared to diameter).  That makes racing sparks more likely.  Reducing coupling fixes racing sparks.  However, low coupling hurts performance.  Try JavaTC to estimate coupling for your geometry.

I'll double check the coupling with JavaTC. I believe I took the picture with a "wide angle" feature so this distorts the proprtions I think, seeing as the secondary coil has an aspect ratio of 1:5 (40mm diameter and 200mm length). Btw, do you know how the program calulates this value? I've seen people reference the program a bunch of times but never managed to find out how it calculates the coupling factor for a specific geometry.

Vge is important to check.  Shows if you have sufficient dead time and fast enough rise and fall times and reasonable over/undershoot.  Diodes across gate resistors are usually necessary for IGBTs.  Add some series resistance to diode if undershoot is too bad.  TVS diodes should clamp undershoot to a reasonable level.  If you want +-30V peak, you will need lower rated voltage TVS diodes for Vge, around 24V rating.  BTW, I like ~19V laptop supplies for gate drive.  Nice compromise between 15V and 24V.

I'm sorry if I wasn't clear enough. Initally I used a 24V regulator for the Gate-drive supply and noted that I had large under and overshoots when I measured the GDT output voltage (with peaks up to +-30V) which I thought might be too much for my IGBTs (seeing as they're rated for Vge of +- 20V max). I then swapped the 24V regulator to a 15V one and observed that the over/undershoot was reduced to +-20V which I believe the IGBTs can handle. But as you said I should probably replace the gate-emitter TVS diodes with ones that have a lower clamping voltage if I want to protect the gate from voltages beyond ~+-20V
[/quote]

Given the safety concerns with floating measurements I think it might be a good reason to buy some differential probes. Will two suffice? I was thinking I could use one to measure the Gate-emitter voltage during operation and one to measure the Collector emitter-voltage. Would I then be able to determine if cross-conduction occurs?

Additionally it takes a suprisingly long time to fix the H-brige so I'd like to make a low inductance PCB

Yes, low inductance, especially to the snubber caps (that are missing now) is important.  Another option without making a "real" PCB is:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886

When I have a circuitboard design i'll post to the forum to make sure I haven't screwed up majorly : )

[davekni]

Do you think it would be easier to find a suitable power Mosfet?

No, finding FETs for 200A will be very difficult.  Fast IGBTs can work, at least with properly adjusted phase lead.  Might be possible w/o phase lead.  W/o phase lead makes low-inductance bridge layout and bypass caps more critical.  Phase lead is a feature of UD2.x and up, not of UD1.3.  I believe UD1.3 can be modified to add phase lead, but I'm reluctant to publish that until I've had a chance to test it with real hardware.

I'm not familiar with using snubber capacitors across Vbus at each half-bridge, I thought they were only used to reduce the power loss in the switching device (while dissappating this removed power in the snubber resistor).

Before finding this forum, to me the term "snubber" referred to an R+C network placed across C-E to reduce switching spikes.  Sounds like you use the same definition.  On this forum, people use the term "snubber capacitor" to refer to what I'd call a bypass capacitor across Vbus.  Look through other builds on the forum.  Such Vbus bypass capacitors (usually called "snubber capacitors" on the forum) are usually 1uF to 5uF each.  I use more and larger bypass caps along with small ones on my bridges, over-kill just because I'm a perfectionist for such.

Btw, do you know how the program calulates this value?

No, I do not know JavaTC internals.  However, I find it's results plenty accurate.  The free finite element program FEMM can handle more unusual cases.  Normal cases that JavaTC covers match FEMM and measurements within +-10% for everything I've tested or simulated, usually within +-5%.

Given the safety concerns with floating measurements I think it might be a good reason to buy some differential probes. Will two suffice? I was thinking I could use one to measure the Gate-emitter voltage during operation and one to measure the Collector emitter-voltage.

Differential probes are expensive.  Most people have at most one.  With none, you can still check Vge and Vce at low voltage using bench supply.  With one, measure Vge and Vce sequentially, triggering on a non-differential probe channel monitoring GDT primary (UD1.3 output) or some other internal UD1.3 signal.  As long as behavior is consistent from one scope trigger to the next, moving a single differential probe to different points is as good as having multiple differential probes.

Would I then be able to determine if cross-conduction occurs?

Probably.  Cross-conduction is easy to see with UD2.x drivers with phase lead.  IGBT switching occurs just before current zero-crossing.  H-bridge output transition is caused by remaining primary current as one pair of IGBTs turns off.  Opposite pair turns on slightly later as current crosses zero.  With UD1.3, IGBT switching occurs slightly after current zero-crossing.  H-bridge output transition is caused by the IGBTs turning on.  Makes it a bit harder to tell if opposite IGBTs are all the way off first or not.  Output voltage spikes are one way to tell.  When you get to this point in testing, please post waveforms.

When I have a circuitboard design i'll post to the forum to make sure I haven't screwed up majorly : )

Sounds good.  As in the H-bridge layout link I posted, the key is overlapping parallel copper planes on the two sides of ECB.  Goal is to block magnetic fields trying to loop around current paths.  Paths with high frequency current switching are the important ones, from bypass capacitors to IGBTs and between low-side collector and high-side emitter within each half-bridge.  Bridge output leads are less important, as they conduct sine-wave primary coil current, not high frequency switching currents.

[Jesperb123]

Hi again!
I think I have a plausible reason for why the right side of the bridge always fails before the left side. I remember reading about uneven leakage inductance and cross conduction on a site called thedatastream where the author (James Pawson) ran some basic simulations showcasing the effects of uneven leakage inductance in a halfbridge driving a resistive load - the TLDR is that the leakage inductance in series with the gate of the switching device introduces a phase shift to one of the gate-signals which can cause a significant amount of cross-conduction.

I ran a similar simulation (with n-mosfets) in LTspice today with a H-bridge and an LC load driven its resonant frequency. I placed 100nH in series with the gates of the mosfets in the left leg and 300nH in series with the gates of the mosfets in the right leg to reflect the fact that the wires going to the right leg of the H-bridge were ~ three times the length of the wires going to the left leg. I used this calculator to estimate the inductance of the twisted pairs https://www.eeweb.com/tools/twisted-pair/ (with D = 0.25mm and S = 1mm which gave ~8.32nH/cm).

The average power dissapated in the right mosfets were about 50% higher relative to the avg. power disappated in the left mosfets. This might explain why the right side keeps failing. Any thoughts?

[davekni]

This might explain why the right side keeps failing. Any thoughts?

Certainly plausible.  Any subtle difference causes slight temperature differences. Temperature rise of left IGBT die may be 90% of the right IGBT die.  That is still enough to make right side fail, shorting supply and saving left side before it fails.
Only other slight asymmetry I notice is bulk cap wires are slightly closer to left side.

I used this calculator to estimate the inductance of the twisted pairs https://www.eeweb.com/tools/twisted-pair/ (with D = 0.25mm and S = 1mm which gave ~8.32nH/cm).

The CAT5 cables I've used are 24AWG (0.5mm diameter).  I've measured inductance to be 625 to 660 nH/m, so a bit lower.  Depends some on the twist pitch, as total wire length is slightly higher with more twists per unit length of twisted pair.  The four pairs are intentionally twisted at different pitches to minimize interference between pairs.

Leakage inductance of GDT can be estimated reasonably by just the inductance of a twisted pair for the length of the winding.  When using a single twisted pair for primary leads, remember that leakage inductance there is 4x as important, as GDT primary current includes current for all four IGBTs.  That is why keeping all four primary twisted pairs all the way back to driver is better.

[Jesperb123]

I wanted to post the low-inductance [I hope : ) ] PCB here before sending it to off to manufacturing in case anyone has some advice on how I could improve it. I tried to follow as many of the design guidelines presented by Dave as possible (i.e making sure current paths are symmetrical and on-top of one another by utilizing perpendicular copper planes). I've also made room for two snubber capacitors placed across the Vbus (with different raster sizes to accomodate the most common film capacitor sizes). I also made it so one can place two IGBT's in parallel for future upgrades.

I wanted to preserve the copper planes as much as possible so I decided to remove the gate-resistors (and TVS diodes) from the PCB assembly. The gate pads are removed from the PCB for the same reason. The additional components will be soldered directly to the IGBT leads (as close as possible to minimize lead length). The H-bridge outputs are placed on top of eachother on different sides. The idea is to use a nylon screw with insulating washers to press two circular crimp connectors to the output nodes (for easy disassembly). The oval slots transfer the output 1 node from the back of the board to the front of the board (and I intend to fill the large oval slots with solder to increase current carrying ability - I figured this would be easier than using a million vias).

[Mike]

It's certainly a unique layout, I commend you for trying something new. In order to minimise inductance, typically you would want to run HVDC+ and HVDC- on top of one another on opposite sides of the board. This is the easiest way to minimising the loop area, encourage the magnetic fields of the current in one conductor to cancel our those travelling in the other conductor, and you have the distributed capacitance from the two planes in close proximity.

Stray inductance on your bridge output will result in voltage spikes on those outputs, the 1.6mm or so of clearance through the PCB is pretty marginal spacing and if the junction gets warm the nylon bolt will relax causing a higher impedance at the junction, causing more heating in what could result in a run away effect. How big a problem this turns out to be will depend on the final current and duty cycle, but given your bridge is potential capable of 700A, it would make me a little nervous.

Best of luck!

[Jesperb123]

It's certainly a unique layout, I commend you for trying something new.

Thanks for the kind words, made my day

Stray inductance on your bridge output will result in voltage spikes on those outputs, the 1.6mm or so of clearance through the PCB is pretty marginal spacing and if the junction gets warm the nylon bolt will relax causing a higher impedance at the junction, causing more heating in what could result in a run away effect. How big a problem this turns out to be will depend on the final current and duty cycle, but given your bridge is potential capable of 700A, it would make me a little nervous.

This seems like a very reasonable concern. I've now removed the through hole (and thus the need for the nylon screw) from the pcb. I'll simply solder the circular crimp terminal to the pads instead (see pictures below).

In order to minimise inductance, typically you would want to run HVDC+ and HVDC- on top of one another on opposite sides of the board. This is the easiest way to minimising the loop area, encourage the magnetic fields of the current in one conductor to cancel our those travelling in the other conductor, and you have the distributed capacitance from the two planes in close proximity.

Yes I've seen many people using laminated busses for their large IGBT inverter setups although i'm sure it works for smaller inverters as well (like mine). I just couldn't figure out how to achieve this when I have to fit two other nodes (the output nodes) on the same 2-layer board while maintaining symmetry (which I've read is very important when paralleling IGBTS). With Dave's method of constructing the four copperplanes I believe the same effect can be achieved  (minimizing loop area and making sure that magnetic fields cancel each other outside the conductors) with my layout since the current paths are roughly on top of eachother. I've (very crudely) drawn the current path (it will "fan out" in reality) through the pcb:


As a side note, I'll use 2oz copper for the board.

Best of luck!

Thanks! I'll keep posting updates to this thread.

[Jesperb123]

I was recently looking at pricing for making the boards and for some reason 2oz 2-layer aluminium PCBs aren't that much more expensive than regular 2oz 2-layer FR4 boards. Since aluminium conducts heat better and is more rigid than FR4 I was thinking that this might be a good option, however i'm wondering if induced currents might become an issue?

If the layout works as intended the fields should cancel outside the conductors but the remaining field between the current paths might cause inductive heating of the board?

[davekni]

It's certainly a unique layout, I commend you for trying something new. In order to minimise inductance, typically you would want to run HVDC+ and HVDC- on top of one another on opposite sides of the board. This is the easiest way to minimising the loop area, encourage the magnetic fields of the current in one conductor to cancel our those travelling in the other conductor, and you have the distributed capacitance from the two planes in close proximity.

The circular idea with radial placement of IGBTs is interesting.  Plane layout is a great circularized implementation of my low-inductance H-bridge tutorial.
Placing HVDC+ and HVDC- (what I usually call Vbus+ and Vbus-) opposite each other is the most conventional way to minimize inductance of Vbus connections.  However, it is not the only low inductance option.  These adjacent planes work well.  The bridge output planes on opposite ECB layer cover the gaps in Vbus planes, blocking most magnetic field that would otherwise pass through the gap between Vbus planes.

I was recently looking at pricing for making the boards and for some reason 2oz 2-layer aluminium PCBs aren't that much more expensive than regular 2oz 2-layer FR4 boards. Since aluminium conducts heat better and is more rigid than FR4 I was thinking that this might be a good option, however i'm wondering if induced currents might become an issue?

Interesting idea.  Inductance would be even lower given the thin insulation.  (Even with FR4, inductance of this layout will be less than inductance of IGBT and capacitor leads, so plenty good enough.)

If the layout works as intended the fields should cancel outside the conductors but the remaining field between the current paths might cause inductive heating of the board?

Induced currents will flow in aluminum core rather than in copper plane on opposite side of ECB.  Aluminum conductivity is lower than copper's, but the aluminum is also thicker.  I'd guess power dissipation will be similar.  Either way, ECB power dissipation is not likely significant enough to be of concern.