Distorted gate waveforms

[prabhatkumar]

Hello everyone,
I am trying to build a full bridge circuit based on the Profdc9 PCB pack. Link : https://highvoltageforum.net/index.php?topic=1898.0
I am using the Phase shifted full bridge topology to control the output power( yes I am aware that the standard interrupter method can be used, but this is a part of my college academics which has put the constraint.
I am using isolated gate drivers NCP51561( again pulse transformer is also a great option, but its difficult to add deadtime there. I have added a deadtime of 400nS (I am not sure if this much is actually required, as the board itself has the resistor bypass by schottky diode on it). I think the gate drivers are doing a decent job of driving these charge hungry devices (compared to MOSFETS) without any buffer while maintaining a fast rise time of 100nS of the gate signal and 50nS of fall time.

The IGBTs which I am using is the FGH60N60SMD, based on the recommended device list on Gao's loneoceans website. All these transistors are mounted on a common large heatsink with isolation pads. For test purposes, I am running everything at 100kHz.
I am using a bus capacitance of 1880uF(470uFx4) to give the DC bus to the bridge.

The problem which I am facing is that when I am running the coil at lower voltage, say 30V, then the gate waveform remains relatively clean from any ringing or distortion( gate resistance of 2.2 ohm). But when I increase the the bus voltage to a larger value( like 80V), then the gate waveforms start getting distorted, as in it turns off when it should have been on. And the distortion increases as I increase the voltage, like 370V DC.

I have also added the optional 440CA TVS diode and the gate 18CA TVS diodes on the PCB, but I have not mounted the snubber network.

From my intial observation, this distortion of the low side switch happens exactly when the other diagonal pair in the full bridge turns on. For loading the bridge, I am using a small transformer with ~4mH of primary inductance. Its not supposed to draw any significant current, I have just added it so that the freewheeling of the body diodes actually takes place(not possible in a resistive load).

Another thing is that without any load also attached, the IGBTS get pretty warmed up, and draw some siginficant current while doing absolutely nothing. But surpirisngly, the output looks pretty much perfect except for some ringing to lead inductance.


Now coming to the waveforms.

Rise time


fall time


With 80V on the bus, yellow is VGS of low side switch and blue is the output.


With 360V on the bus, yellow is VGS of low side switch and blue is the output.

Any help/ Suggestions are greatly appreciated. Thank you.

[davekni]

By your last 360V scope capture, anomalous gate transitions are clearly full swing.  Only way to get that is with changes to NCP51561 logic input levels.  (Remotely possible that cause could be glitches in NCP51561 supply pins if bypass capacitors are too far away and/or not routed well on ECB.)  Likely an issue with unintended coupling from H-bridge outputs back to logic circuitry.  First suspect is circuitry generating floating gate drive supply voltages (+16/-8V or so) for high-side gates.  Next most likely cause is general layout and wiring issues, parasitic inductances especially.  Perhaps a combination of the two, capacitance across high-side gate supply input-to-output creates current spikes and parasitic inductance allows those current spikes to develop sufficient voltage drop to disrupt logic.

[prabhatkumar]

Thanks for those pointers, DaveKni. Yes, I do have the power bus wires running just next to the gate signals. I was forced to do this as I am not able to find a way in which the bus wires length could be minimised. If possible can someone please point out few examples for the board which I am using, I.e the full bridge transistor trom the Profdc 9 PCB pack.
The supply and bypass capacitors are properly soldered next to the IC. I am using a TI reference design for the isolated gate drivers as it is, only thing I changed is that I made a home brew adapter on a protoboard, to route the signals to the the gate pins of the power PCB, to which I soldered female header pins for a snap in fitting. I also added isolated supplies for the upper and lower switches on the same protoboard which also have generous amounts of decoupling(10u, 1u).
I will send pictures of the setup soon since I am not in college right now.
I also have Si82398 gate drivers, which seems to have some kind of de glitcher inside, so should I try that ?
Another interesting observation is that, the time when the gate drive signal is corrupted in close 400ns, which surprisingly is the dead time in my case, so does this indicate something ?
Thank you

[davekni]

Yes, I do have the power bus wires running just next to the gate signals.

If caps on H-bridge board from Vbus+ to Vbus- are sufficient, power bus wiring isn't as likely to be an issue, especially for your low-current testing.  I'd be more concerned about H-bridge output voltage routing.  This includes high-side gate drive, as high-side emitters are H-bridge outputs.
What are you using to generate high-side gate power?  If it is one of the commercial modules intended for high-side gate drive, it should have good isolation.

BTW, does your 4mH transformer connected directly across H-bridge outputs?  If so, any imperfection in 50% duty cycle creates DC component to output voltage which may saturate your transformer.  (I presume you selected a transformer than can handle +-360V at 100kHz, so only concern is added DC.)

I am using isolated gate drivers NCP51561( again pulse transformer is also a great option, but its difficult to add deadtime there. I have added a deadtime of 400nS (I am not sure if this much is actually required, as the board itself has the resistor bypass by schottky diode on it).

Yes, 200ns should be plenty.  With driver-chip dead time and negative drive, gate diode is likely unnecessary too.  No particular reason to change, however.

I also have Si82398 gate drivers, which seems to have some kind of de glitcher inside, so should I try that ?

NCP51561 typically ignores inputs less than 15ns.  Si82398 with optional glitch filter ignores 30ns.  I suggest focusing on finding the glitch source rather than filtering it out.

Another interesting observation is that, the time when the gate drive signal is corrupted in close 400ns, which surprisingly is the dead time in my case, so does this indicate something ?

Likely indicates internal NCP51561 architecture rather than anything relevant.  Input glitch likely starts dead-time timer.  Timer likely forces both outputs low for 400ns, even though the end of the glitch would logically re-enable the same IGBT and thus theoretically not need any dead-time.

I will send pictures of the setup soon since I am not in college right now.

Yes, pictures will hopefully allow more helpful suggestions.

Good luck with your project.  You are gaining valuable experience in how real-world engineering works.  Most designs have subtle issues that aren't obvious from basic circuit analysis.