Basic Gate driving doubts

[prabhatkumar]

Hi there everyone,
I have asked several doubts regarding gate driving earlier on this forum and each of them was asked with the intention of making my coil work.
Now, I have sought of taken a dive into the gate driving fundamentals as I have a college reasearch project, where I am desinging a gate driver. So, I have few doubts with respect to the gate driving techniques used in the UD2.7 board.
 They are as follows:

1) In this schematic from ud2.7, Gao says that the main curernt carrying capacitor is the C30( 2.2uF ceramic). So usually for damping the spikes due to inductances and other issues, we put a series resistor with the capacitor. But here he puts a resistor in parallel( and a also a DC blocking cap to prevent resistor burnout in event of saturation). So please me know the reason for placing the resistor in parallel).
2)Now, comming to the buffer stage, the PMOS is capacitvely coupled. Why is it done so? If it would have been in a NMOS then the level shifting was neccsary. But here since the PMOS is already having a LOW VGS(threshold) of like (-1.6V) i.e they would turn off anyting greater than -1.6V.
3)Also, I have doubt reagrding the winding of the pulse transforrmer. I have a very limited sense of understanding the science of transformers and their coupling, so please don't get angry on me
The doubt is that I understand we have to wind a certain of number of turns(depending on core size, material and operating frequency) to prevent saturation of the transformer. But what is the effect of increasing the number of turns greater than mimimum?
(which is usually the case since we generally wind to the fill the entire core). I have read previously on this forum on this regarding that it will increase the magnetizing inductance and hence the curent also, but I do not understand it.
4) This last question is sort of application oriented. I wish to have deadtime in my final circuit and hence I would generate my signals with deadtime from the controller which I am using. But is it possible to have deadtime through a pulse transformer. I have once tried but at the output all I got was ringing in the output during the deadtime. I thought that passing a zero level through the transformer during deadtime was saturating it, hence I left that part till now. But now as I see it, I think adding deadtime is possible. Also is it possible to have the IGBT's gate pulled to VEE(-7V to -15V) during deadtime?Usually I think it's just pulled to zero volt, but I wanted to have some better noise immunity.   
It would be of great help if you all answer such basic questions.
Thank you in advance.

[davekni]

In general, I recommend lots of experimenting with simple circuits and simulation in LTSpice or other analog simulator.  Will help with your understanding of these specific questions and electronics in general.

C30( 2.2uF ceramic). So usually for damping the spikes due to inductances and other issues, we put a series resistor with the capacitor. But here he puts a resistor in parallel( and a also a DC blocking cap to prevent resistor burnout in event of saturation). So please me know the reason for placing the resistor in parallel).

Purpose here is to damp resonance of C30 with parallel inductance of GDT.  More common snubber circuits are to damp smaller parasitic inductances (transformer leakage inductance and/or wiring inductance).  Simulation is the best option for understanding this more.

2)Now, comming to the buffer stage, the PMOS is capacitvely coupled. Why is it done so? If it would have been in a NMOS then the level shifting was neccsary. But here since the PMOS is already having a LOW VGS(threshold) of like (-1.6V) i.e they would turn off anyting greater than -1.6V.

Buy a couple cheap PFETs.  Experiment with them and a couple resistors, batteries or bench supply, and volt meter.  Do the same for NFETs too and compare results.  Once you understand FET behavior, then try simulation.  Or the answer may be clear by then.

3)Also, I have doubt reagrding the winding of the pulse transforrmer. I have a very limited sense of understanding the science of transformers and their coupling, so please don't get angry on me
The doubt is that I understand we have to wind a certain of number of turns(depending on core size, material and operating frequency) to prevent saturation of the transformer. But what is the effect of increasing the number of turns greater than mimimum?
(which is usually the case since we generally wind to the fill the entire core). I have read previously on this forum on this regarding that it will increase the magnetizing inductance and hence the curent also, but I do not understand it.

This is a more subtle question, one I've seen in some form before.  Inductance increases, reducing current (not increasing current).  That is generally good.  The down side is that leakage inductance increases too.  More leakage inductance requires larger gate resistor values to avoid excess overshoot, so slows down gate voltage transitions.

4) This last question is sort of application oriented. I wish to have deadtime in my final circuit and hence I would generate my signals with deadtime from the controller which I am using. But is it possible to have deadtime through a pulse transformer. I have once tried but at the output all I got was ringing in the output during the deadtime. I thought that passing a zero level through the transformer during deadtime was saturating it, hence I left that part till now. But now as I see it, I think adding deadtime is possible. Also is it possible to have the IGBT's gate pulled to VEE(-7V to -15V) during deadtime?Usually I think it's just pulled to zero volt, but I wanted to have some better noise immunity.

Yes, deadtime is possible and simple.  Just delay input to one of the UCC driver chip inputs relative to the other.  That produces a period of 0V into GDT.  GDT leakage inductance is more critical in this case, as a transition to 0V rather than -15V is more sensitive to overshoot and ringing.  One nice side of adding dead-time this way is that gate drive power consumption is cut in half (half the DC current into UD2.7 for given frequency and gate capacitance).
Concerning deadtime with also having negative Vge, I can't think of any reasonable way to do this with a GDT.  Needs floating gate supply voltages and isolated drivers.  This is the standard solution for commercial systems driving IGBT bricks.

[prabhatkumar]

Thank you for answer Davekni. I am convinced with all the other answers you have except for one.
I understand simualtion is the right way of understanding such circuits. But the question about the capacitive coupling of the PMOS from NMOS gate, will choosing drivers which have split high and Low outputs for IGBTS better ?. I have seen several reference designs across different manufacturers like TI and Broadcom getting away with just directly tying the gates of the NMOS and PMOS with a additional gate damping resistor.
Also as I have asked before about the cross conduction and slight heating of the FETs in the buffer stage, is it due to the capacitive coupling which causes the slow rise/ fall times ?
If it’s because of this capacitive coupling then I would simply switch to BJT based designs as a slight VCE drop won’t affect me.

[davekni]

I understand simualtion is the right way of understanding such circuits.

Yes.  Cross-conduction will show up in simulations.  So will necessary conditions for direct connection to FET gates.  For a hint: Look at supply voltage of driver chip and of FETs.  But do the simulations even if my hint gives away the answer.  Much more important to understand than to have the correct answer.