Author Topic: Performance issues regarding phase angle in SSTCs  (Read 278 times)

Offline Max Seiringer

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Performance issues regarding phase angle in SSTCs
« on: January 08, 2022, 03:21:31 PM »
Hi folks!
I'm buildung a small solid state teslacoil using a 74HC14 feedbacksystem with a current transformer. First off some detail:
The circuit diagram is pretty similar to the Kaizer SSTC II. I am driving my coil with a IRFP460 fullbridge at 30VDC at the moment. Sadly, there is currently no safe way to conduct tests at higher voltages, the variac is out of order.
I use a sheet of aluminum foil as an earth plane, since i live in a small apartment and no proper ground is available.
The cores used for the GDT and the CT are 3E25 and N30. The primary coil features 8 windings and the secondary coil just above 1000 turns. The resonant frequency is about 270kHz.
The Interrupter is based on an Arduino Micro and has audio capabilities. It is connected to the driver logic via a fiber obtic cable.





The setup works to some extend. The arcs come in at about 1cm at 30VDC while drawing roughly 3A in CW mode. Not too great results considering the coil is driven by a fullbridge.
I measured across the primary with one probe and used a second probe as an antenna to pick up the signal from the secondary.
It seems that the voltage across the primary coil leads the voltage at the secondary. This results in a 60° phase angle between the two signals.



What phase angle would be ideal for a solid state teslacoil? Could the performance issues be fixed by adding phase compensation to the circuit or is there another culprit?

Kind regards
Max

Offline davekni

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Re: Performance issues regarding phase angle in SSTCs
« Reply #1 on: January 09, 2022, 01:20:40 AM »
Nicely paired primary lead wires.  That keeps effective coupling high by avoiding parasitic inductance.

In general, your build looks fine.  My guess is that you just need more power (higher input bus voltage).  Ideal phasing between primary and secondary voltage is 90 degrees.  60 is close enough.  Adjusting to 90 would increase input current a bit (~15%) and therefore increase power a bit at your fixed 30Vdc input.

To avoid possible issues when increasing power, I suggest soldering GDT output leads closer to the FET packages, especially the FET source leads.  Otherwise wiring inductance is shared between high current path and gate drive, leading to unwanted voltage distortion of gate drive.
David Knierim

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Re: Performance issues regarding phase angle in SSTCs
« Reply #1 on: January 09, 2022, 01:20:40 AM »

 


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