Author Topic: DRSSTC strange gate waveform  (Read 842 times)

Offline Rapy2

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DRSSTC strange gate waveform
« on: October 29, 2021, 10:10:37 PM »
Hi there,
I'm just working on my medium sized drsstc. After a few stupid mistakes when I had to replace igbts to-247 in a double full bridge, I finally decided to replace to-247 with bricks. I bought SKM200GB125D from ebay and they seems to work just fine. I did some basic measurements and found a very strange gate waveform. It looks like the effect of reverse transfer capacitance. The voltage at the gate gradually increases, then reaches the plateau point when the transistor starts to switch and the voltage drops sharply. At the beginning of the pulse (less than 50 A), the drop is greatest, down to zero volts (scope 1). At the end of the pulse (roughly 600 A), the drop is smaller, but still too much for my taste (drops down to 11 volts)(scope 2). It looks like the gate waveform follows Vce waveform. With my phase lead the spikes at Vce are the highest at the beginning of the pulse and the smallest at the end. Right now the gate resistor is 4,7 ohms. I tried to decrease the gate resistance to 3 ohms, but it didnĀ“t help. The voltage overshot up to 30V, the drop was almost same 13-17 volts, so it dropped to around 15V and not to 11 like with 4,7 ohms. I am attaching pictures. Thanks for any advice :)

Offline Vtroxi

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Re: DRSSTC strange gate waveform
« Reply #1 on: October 30, 2021, 12:14:18 AM »
Hi,

even though I am not an expert on these issues, I can still think of two common reasons for oscillations of the gate signal.
The first one would be an improperly tuned phase lead - a gate signal often looks quite bad without soft switching.
Can you send a few scope plots of the primary current vs the inverter output?

The second reason that comes to my mind is gate resistance and GDT leakage inductance. Gate resistors have several important purposes: they limit the charging current, add a dead time (preventing shoot through, etc.), and also help to dampen unwanted oscillations of the gate capacitance with the GDT inductance.

Your 4.7 ohms of gate resistance might be not enough for decent dampening of oscillations - you can probably try 6 or 8 ohms and see if that improves the signal.
But I'd recommend trying to tune the phase-lead first. Because you might get rid of the oscillations anyway.

This page also has a few general tips when it comes to gate signals: http://www.richieburnett.co.uk/temp/gdt/gdt2.html

If you get rid of the ringing but still encounter 30V overshoots after everything else is properly tuned, you could add 20V TVS diodes across the gates to clamp the voltage.

I hope I could help you a bit :)

Best regards,

Vtroxi

Offline Rapy2

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Re: DRSSTC strange gate waveform
« Reply #2 on: October 30, 2021, 12:44:09 AM »
Hi Vtroxi,
thanks for your reply :)

I think my phase lead is tuned to the point where it should be just fine. I tuned it with not only Vce on my scope, but also with gate waveform and I tried to set it to the point, where the voltage drop is the smallest, but this was the best I got from it. I am attaching scope shot with Vce vs Primary current at roughly 600 A.


About the gate resistor, I originally tested it with 10 ohms, it was my first guess. But the gate waveform was too much rounded and rise and fall times much slower.

Thanks for the link :)

I think my problem is somewhere else. Oscillations at the beginning of the pulse make me sense, because the phase lead is tuned for lowest spikes at highest current. At the beginning of the  cycle its not tuned properly, it get to the right phase with increasing current. Oscillations at the beginning are not a problem because the current is low. Problem is the high voltage drop due to a reverse transfer capacitance. But I guess it has something to do with right gdt and gate resistor selection to reduce this effect.

Greetings,
Rapy2

Offline davekni

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Re: DRSSTC strange gate waveform
« Reply #3 on: October 30, 2021, 05:01:35 AM »
Looks to me like insufficient phase-lead.  Vce should be switching due to remaining primary current before zero-current.  The Vge glitches are likely due to Vce transitions, which should be earlier, before Vge reaches threshold voltage.

Also, most builds include diodes across gate resistors to speed IGBT turn-off.  That does increase Vge negative transients, so Vge TVS diodes may be required too.  (Vge TVS diodes are a good idea anyway to protect IGBTs from ESD or other random transients.)

4.7 ohms looks reasonable.  No reason to go higher.
David Knierim

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Re: DRSSTC strange gate waveform
« Reply #4 on: October 30, 2021, 05:09:44 AM »
Also, most builds include diodes across gate resistors to speed IGBT turn-off.

Could it also be a cross-conduction issue caused by the lack of turn-off diodes?
It would explain that huge Miller capacitance effect.
In my opinion, IGBTs should always have those diodes since their t_off and t_on is so asymmetric.
Marek Novotny
Czech Republic, Czech Technical University in Prague
www.uhvlab.org

Offline davekni

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Re: DRSSTC strange gate waveform
« Reply #5 on: October 30, 2021, 05:44:52 AM »
Quote
Could it also be a cross-conduction issue caused by the lack of turn-off diodes?
It would explain that huge Miller capacitance effect.
In my opinion, IGBTs should always have those diodes since their t_off and t_on is so asymmetric.
Possible, but the waveforms don't look like cross-conduction to me.
Diodes are not always necessary.  Bipolar Vge drive has inherent dead-time due to finite slew rate.  That can easily be sufficient depending on Vge slew rate and IGBT speed.  It is good to have some dead-time margin, as IGBT turn-off time increases when hot.  However, excessive dead time requires more phase-lead to keep turn-on at or before zero-current.  That increased phase-lead means IGBT turn-off is at higher current, so increases turn-off losses.
However, I agree that diodes are wise.  If dead-time is too long with diodes, then decrease gate resistance to increase Vge slew rate and thereby reduce dead time.  If low gate-resistance causes overshoot, then fix that with Vge TVS diodes and/or reducing GDT leakage inductance (shorter leads, one primary for each secondary with primaries individually twisted to driver terminals, etc.).  Also, check the IGBT brick specifications for value of internal gate resistance.  Sometimes external overshoot doesn't mean internal Vge overshoot due to internal gate resistors.
« Last Edit: October 30, 2021, 05:56:06 AM by davekni »
David Knierim

Offline Rapy2

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Re: DRSSTC strange gate waveform
« Reply #6 on: October 30, 2021, 10:48:11 AM »
Hi,
thanks for replies  :)
I am still not sure that its caused by insufficient phase lead. I tried to set the phase lead with 3 different inductors and this is the best possible phase lead.

For now, I just wanna try to rebuild my gdt with just one bigger core and more turns than just 5. I wonder what it will do.


Offline Hydron

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Re: DRSSTC strange gate waveform
« Reply #7 on: October 30, 2021, 05:39:20 PM »
I haven't looked closely at your setup, but I would also say that you have to be careful with probing to avoid seeing things that aren't there. Make sure that you don't have a big loop area between your probe and ground point (wrapping the ground wire around the probe to shorten it is a common tactic), and see if you notice any difference.

Offline Rapy2

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Re: DRSSTC strange gate waveform
« Reply #8 on: October 30, 2021, 06:39:28 PM »
I haven't looked closely at your setup, but I would also say that you have to be careful with probing to avoid seeing things that aren't there. Make sure that you don't have a big loop area between your probe and ground point (wrapping the ground wire around the probe to shorten it is a common tactic), and see if you notice any difference.

Thank you for your advice  :) I never probe like this. I will try it and see if it will make any difference.

Offline davekni

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Re: DRSSTC strange gate waveform
« Reply #9 on: October 30, 2021, 07:12:09 PM »
Quote
I am still not sure that its caused by insufficient phase lead. I tried to set the phase lead with 3 different inductors and this is the best possible phase lead.
Concerning phase lead, how are you defining "best"?  Lowest switching losses occur when Vce transitions occur slightly before zero current.  One pair of IGBTs turn off, then remaining current causes Vce transition (charges collector-emitter capacitance), then the opposite pair of IBGTs turn on at zero-current time (or very slightly before zero-current).  The IGBTs turning on have 0 Vce at turn-on (actually negative ~1V Vce by the internal diode drop), so there is no turn-on switching loss.  If scoping Vce carefully, the transition after turn-on can be seen as Vce going from -1V to +1V (IGBT forward drop).  Turn-off is slightly earlier with some current, so there is a bit of switch-off energy.  Not that much, since current is low and dropping.

If phase lead is close but not quite enough, Vce will show triple-transitions.  First transition is at turn-off time before current reaches zero.  Second transition occurs as current reverses and starts charging Vce again.  Third transition occurs when opposite IGBTs turn-on.  If you see these triple-transitions, ideal phase lead is slightly more, not slightly less, to avoid the triple-transitions.  (This presumes sufficient dead-time.  If dead-time is short or non-existent, there will be no triple-transitions even with switching right at zero-current.)
David Knierim

Offline Rapy2

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Re: DRSSTC strange gate waveform
« Reply #10 on: October 30, 2021, 08:48:37 PM »
I tried to set the phase lead such a way that this gate waveform has the smallest ripple and the pictures I send were the best result I got from it. Vce at this phase lead setting looks fine, no triple transitions, just small voltage spikes and almost no spikes (less than 20V) when the current is the highest.

Thank you for very nice explanation of the phase lead  :)

Right now I tried it with new bigger gdt with 12 turns insted of 2 gdt with 5 turns each and it seems to do better. Gate waveform looks better at the highest current, but when the pulse start, it still oscillates much so it reaches almost 0V during the oscillation.

Offline AstRii

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Re: DRSSTC strange gate waveform
« Reply #11 on: October 30, 2021, 08:52:33 PM »
Gate waveform looks better at the highest current, but when the pulse start, it still oscillates much so it reaches almost 0V during the oscillation.

I'd try to use common mode filter while probing, maybe it's just an artifact from the switching. If not, I'd try to reduce leakage inductance of the GDT which usually causes high frequency oscillations.   
Marek Novotny
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Offline davekni

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Re: DRSSTC strange gate waveform
« Reply #12 on: October 30, 2021, 09:47:41 PM »
Quote
Right now I tried it with new bigger gdt with 12 turns insted of 2 gdt with 5 turns each and it seems to do better. Gate waveform l
More GDT turns actually makes GDT leakage inductance worse.  GDT must have enough turns to avoid core saturation.  Beyond that number, more turns increases wire length which increases leakage inductance.  Most of my GDTs use large cores with only 2 or 3 turns.
Yes, a single GDT is generally best, unless running pulse-skipping where two are necessary.
David Knierim

Offline Rapy2

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Re: DRSSTC strange gate waveform
« Reply #13 on: October 30, 2021, 11:28:58 PM »
Well that makes sense with the leakage inductance, but actually the bigger gdt with more turns makes it better, not ideal but better.

Offline davekni

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Re: DRSSTC strange gate waveform
« Reply #14 on: November 02, 2021, 05:11:49 AM »
Quote
I tried to set the phase lead such a way that this gate waveform has the smallest ripple and the pictures I send were the best result I got from it. Vce at this phase lead setting looks fine, no triple transitions, just small voltage spikes and almost no spikes (less than 20V) when the current is the highest.
One more thought on this:  Perhaps Marek is right about insufficient dead time, and the resulting bit of cross-conduction (shoot-through) makes phasing look better when late (less phase lead).  Not sure I could exactly explain initial scope plots with this theory, though.
David Knierim

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Re: DRSSTC strange gate waveform
« Reply #14 on: November 02, 2021, 05:11:49 AM »

 


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[Solid State Tesla Coils (SSTC)]
davekni
January 07, 2022, 05:15:38 AM
post Re: DRSSTC tuning
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
January 07, 2022, 05:01:21 AM
post Re: How to prevent secondary to secondary to primary arcs?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
January 07, 2022, 04:59:59 AM
post Tophat QCW 1
[Dual Resonant Solid State Tesla coils (DRSSTC)]
dbach
January 07, 2022, 02:27:35 AM
post How to prevent secondary to secondary to primary arcs?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
dbach
January 07, 2022, 02:19:40 AM
post Re: General Questions
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Mads Barnkob
January 06, 2022, 09:33:06 PM
post Re: First SSTC based on profdc9 PCB Pack
[Solid State Tesla Coils (SSTC)]
alan sailer
January 06, 2022, 06:09:39 PM
post Re: DRSSTC tuning
[Dual Resonant Solid State Tesla coils (DRSSTC)]
kubajed
January 06, 2022, 04:48:22 PM

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