GDT waveform has big undershoot

[SalinsLV]

Hi!

My goal is to achieve the perfect GDT waveform to power my DRSSTC. After many experiments, I improved the waveform to the point that I flattened overshoot, however I am struggling to figure out how to flatten undershoot. I made circuit analysis as seen below:


Waveform with 20R at gate (flattened overshoot):


Waveform with 10R at the gate (with overshoot):


Diode/resistor change only made difference to overshoot. Undershoot remains the same even after resistor/diode change. The whole circuit is built on a breadboard, however I made connections as close as possible. All the details should be in the circuit analysis attachment.

Any ideas on how to eliminate undershoot or at least minimize it?

[alan sailer]

I am pretty sure that this is normal and you really can't do anything about it. I see it my coil and it is working just fine.

The diode (D2) that is across the gate resistor will bypass it during the negative going part of the waveform.
The result would be under damped (overshoot).

I can speak from personal experience that the search for the perfect waveform can be a real drag. Figuring out what is important
is a better goal :-)

Cheers.

[davekni]

As Alan said, those waveforms are fine.  The overshoot is not enough to violate FET Vgs maximum limits, and the ring-back is not significant (not enough to turn the FET back off after the rising Vgs edge and initial overshoot).

If you still want less overshoot, there are two options.  One is to add resistance in series with the gate diodes.  Some designs do that.  The other option is to reduce GDT leakage inductance and wiring inductance to and from the GDT.  If the GDT windings and/or the input and output leads aren't tightly paired (ie. twisted together), then there is more parasitic inductance than necessary.

[T3sl4co1l]

It's asymmetric because there's no coupling capacitor on the primary.

Transient response is the RLC series resonant circuit between driver, GDT leakage inductance, series resistance (including driver and gate resistor), and gate capacitance.  This is critically damped when R = sqrt(L/C), overdamped when R is higher, and rings when lower (which seems to be the case here).

Leakage inductance is determined by winding length and geometry.  If you start with twisted pair for example, that has a characteristic impedance of ~100 ohms, and 0.5uH/m inductance.  Use pairs in parallel to reduce inductance, and prefer a thicker core cross section to reduce number of turns (while increasing turn length somewhat).  Pot cores are excellent for this.

Particular advantage is had from twisting twisted pair, to make a "star quad".  Consider the cross section, there are four wires in a circle.  Assign them P, S, P, S going around the circle.  This has closer to 25 ohms impedance, so quarter the inductance of a single pair, or half of two independent pairs in parallel.  Efficient!

Lower impedances come at the cost of capacitance, which reduces CMRR and dV/dt of the drive circuit.  This can be improved with a common mode choke (which is really only needed for the high side, mind).  Construct it exactly the same way, but wire it sideways (so the windings are in series to the gate, in phase, instead of as an isolation transformer).  This comes at the cost of more LL, of course.

Note that drive current is fairly modest, so you can do a fine job with say wirewrap wire, or even enameled if you don't need too much voltage isolation (or get really good wire, like high temp or triple-insulated).  Saves space, more turns on a smaller core, etc.  The resistance just adds with the other resistors.

Tim

[SalinsLV]

Particular advantage is had from twisting twisted pair, to make a "star quad".  Consider the cross section, there are four wires in a circle.  Assign them P, S, P, S going around the circle.  This has closer to 25 ohms impedance, so quarter the inductance of a single pair, or half of two independent pairs in parallel.  Efficient!

I have twisted 3 wires and wound them around the core. I assume that ethernet cable would work the best since most of them have twisted pairs inside + shielded.

If you still want less overshoot, there are two options.  One is to add resistance in series with the gate diodes.  Some designs do that.  The other option is to reduce GDT leakage inductance and wiring inductance to and from the GDT.  If the GDT windings and/or the input and output leads aren't tightly paired (ie. twisted together), then there is more parasitic inductance than necessary.

I have twisted 3 wires together (primary, secondary1, secondary2).
Currently my GDT looks like this:

The diode (D2) that is across the gate resistor will bypass it during the negative going part of the waveform.
The result would be under damped (overshoot).

I removed D2 and the undershoot is gone:


Waveform rise time:


Waveform fall time:

I can speak from personal experience that the search for the perfect waveform can be a real drag. Figuring out what is important
is a better goal :-)

I didn't achieve the "perfect" waveform, however without the diode I have no undershoots and with 20R resistor the overshoot is also gone. I think that I'm ready to assemble small test bridge with IRLZ44N mosfets and if those work, then proceed with IRFP460.

[alan sailer]

Just a note that the diode is there to reduce the IGBJT turn-off delay.

I'd imagine that if the turn-off delay is too long you could run into timing
problems with other devices in the bridge ie in an H-bridge, the high and
low side transistors conducting at the same time, otherwise known as
a short :-)

Cheers.

[Twospoons]

You can also try this arrangement:



You get damping of the GDT with the 20 ohms, and faster turnoff thanks to the current gain of the transistor. It wont give you negative gate drive though, which can be useful sometimes.

[davekni]

You can also try this arrangement:

Need a PNP such as 2N2907 or MMBT2907 for that, not 2N3904.  Nice circuit idea otherwise.

I'd imagine that if the turn-off delay is too long you could run into timing
problems with other devices in the bridge ie in an H-bridge, the high and
low side transistors conducting at the same time, otherwise known as
a short :-)

Agree.  With FETs for the bridge switches, there may be sufficient dead-time without a diode.  If using IGBTs, a diode is almost certainly needed to provide sufficient dead-time.

[Twospoons]

Yeah, that was not meant as a suggested part - its just the default PNP that Simetrix sticks in. I should have deleted the part number.

[davekni]

Yeah, that was not meant as a suggested part - its just the default PNP that Simetrix sticks in. I should have deleted the part number.

Odd.  Is Q2N3904 really a PNP?  2N3904 is very common NPN.  Can't find any data on Q2N3904.

[SalinsLV]

Thanks for the replies!

You can also try this arrangement:



You get damping of the GDT with the 20 ohms, and faster turnoff thanks to the current gain of the transistor. It wont give you negative gate drive though, which can be useful sometimes.

I used that arrangement with BC640 transistor and got this waveform:


I am not quite sure as to what is responsible for that little peak at the bottom. The peak is dV = 3.2V. It shouldn't be enough to turn IRLZ44N or IRFP460N completely on, however the peak reduces duty cycle to 42% which before was close to 50%.

[T3sl4co1l]

There uh, should be a ~1k resistor in series with the transistor base.  The problem is the C-B junction shorts out the GDT for negative going voltages, heavily loading it (and probably shifting it towards saturation).

Tim

[Twospoons]

More likely its taking time to turn the transistor off after the CB junction gets forward biased - bjts perform pretty badly in that mode as I recall.  I ran a sim without the transformer and got the same turn on delay step.   It can be fixed with a Schottky diode in series with the collector to prevent the CB junction from getting forward biased.

[Twospoons]

Odd.  Is Q2N3904 really a PNP?  2N3904 is very common NPN.  Can't find any data on Q2N3904.

try 2n2904