Author Topic: HFSSTC design help and questions  (Read 719 times)

Offline Power-Max

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HFSSTC design help and questions
« on: June 27, 2021, 08:47:55 AM »
I got a whole bunch of FCA35N60 MOSFETs, rated 600Vds and 90mOhms. Although the capacitance are a bit high on it.

I was thinking about making one of those fancy HFSSTCs with it. I wound a secondary and it clocks in at around 7-8 MHz when energized from a function generator.

The circuit I'm using is the very simple one with the DC bias voltage applied to the gate, a small capacitor on the gate connected to ground, with a series LC primary connected drain to gate.

The big problem with this type of circuit seems to be the the unregulated feedback. MOSFET gates are notoriously picky about voltages, and I have to tread carefully so as not to overdrive the gate or exceed 24Vpeak-peak or thereabouts. I thought about redesigning the circuit to operate as common gate, so that the input impedance is very low and the energy gets recycled into the oscillator, but the problem is it's stable (I think common base amplifier is not inverting and hence stable) I need to find a way to invert the phase.

But anyways, regarding the normal circuit, should the ratio of the additional gate-source capacitance and the series LC capacitance be conserved? I most versions of the schematic I came across appear to use 100pF for the tank capacitor and ~4nF for the gate-source shunt. Can these values be scaled proportionally to increase or decrease the operation frequency? I already killed a few of my FETs messing about lol
« Last Edit: June 27, 2021, 08:27:56 PM by Power-Max »

Offline davekni

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Re: HFSSTC design help and questions
« Reply #1 on: June 27, 2021, 06:48:17 PM »
FCA34N60 looks like a fine part for HFSSTC use.  100pF to 4nF is 40:1 ratio.  Adding in ~1.3nF of gate capacitance gives 100pF to 5.3nF or 53:1.  20Vpp on the gate allows only 20 * 53 = 1060Vpp on primary coil.  That seems a bit low, but I don't know your specific design.

To avoid frying parts, start with simulation, LTSpice or other such program.  Much easier to iterate designs in simulation than with physical parts.

TVS diodes gate-to-source can help.  They will quickly overheat if driven too hard, but will protect FETs from transient gate over-voltage.

Make sure the 4nF (or whatever you end up with) capacitor has low inductance and is connected directly to the FET source.

Are the FETs frying with just gate-source fried, or drain-source or all three?  If the issue is excess gate voltage, usually only gate-source shorts.  The FETs are specified at +-30Vgs maximum, higher than many FETs.  Your issue may be excess drain voltage or excess power, which are more likely to result in drain-source shorts (and often gate too, so all three pins shorted).
« Last Edit: June 27, 2021, 09:52:44 PM by davekni »
David Knierim

Offline eli

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Re: HFSSTC design help and questions
« Reply #2 on: July 18, 2021, 09:33:40 PM »
just add a zener, it hasn't too many capacitance to mess something up. my design uses two 12v zeners back-to-back. not a supressor, it has a big capacity. also, with 600v d-s you will be able to supply it 70v max, my irfp260 drain sees 350v on it at just 35v, i still don't know why it doesn't burn. anyway, it should be good enough. zeners must be as close to gate and source as possible. also, about design improvements, make the gate voltage divider work from separate 12v source, that way you can interrupt it, ramp it and make a lot of nice stuff. the tuning will be much easier with some scope. good luck:D

Offline Power-Max

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Re: HFSSTC design help and questions
« Reply #3 on: July 26, 2021, 03:29:32 AM »
just add a zener, it hasn't too many capacitance to mess something up. my design uses two 12v zeners back-to-back. not a supressor, it has a big capacity. also, with 600v d-s you will be able to supply it 70v max, my irfp260 drain sees 350v on it at just 35v, i still don't know why it doesn't burn. anyway, it should be good enough. zeners must be as close to gate and source as possible. also, about design improvements, make the gate voltage divider work from separate 12v source, that way you can interrupt it, ramp it and make a lot of nice stuff. the tuning will be much easier with some scope. good luck:D

Yeah I keep frying the FETs. :(

I have to walk a very thin line with the ratio of the capacitors to prevent exceeding the Vgs rating of the MOSFET. I thought about adding a zener diode but the capacitor divider with the high reactive currents form a very low impedance drive and clamping the voltage would seemingly result in blowing the zener diode. If there was a way to dynamically adjust the capacitor divider ratio as the oscillation grows to full magnitude that'd be ideal! I came up with some pretty convoluted ideas in LTspice but at these frequencies propagation delay is a serious concern that has a massive impact on performance.

Offline davekni

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Re: HFSSTC design help and questions
« Reply #4 on: July 26, 2021, 04:25:03 AM »
Took another look at your initial post and my response.  The link in the first post points to a data sheet for an IGBT, FGH60N60SMD.  I see data sheets for FCA35N60 at DigiKey (and others):
http://www.onsemi.com/pub/Collateral/FCA35N60-D.pdf

Looks like my response was based on the correct data sheet, but I made a factor-of-10 error :(  Average gate capacitance (total gate charge divided by gate voltage swing) is 139nC / 10V = 14nF, not 1.3nF as I'd said.  Combined with typical 1.4 ohms of internal gate resistance gives 20ns delay.  That may be too slow for HFSSTC use, except perhaps at the lower-frequency end of HFSSTC.  Gate resistance causes two other issues besides delay.  Gate power dissipation can easily get as high as drain dissipation.  I don't know enough about FET internal construction, but that level of gate power may be frying the FET rather than excess gate voltage directly.  The other issue is that 14nF internal capacitance is a major factor compared to 4nF external capacitance.  That can be handled by an appropriate value of feedback capacitor.

FCA35N60 gate capacitance is similar to that of the often-used IRFP460.  It is certainly possible to design around the gate capacitance.  Gate resistance is more of a problem.  The IRFP460 data sheet does not specify internal gate resistance.  Perhaps it is low, or at least some of the counterfeit IRFP460 parts have low internal gate resistance.

My apologies for mistakenly encouraging work with a FET that may be marginally useful for HFSSTC.

You may be able to clamp gate voltage with several parallel 10V 1500W TVS diodes, perhaps with 1N5817 diodes in series to reduce capacitance.  (1500W is peak power rating.  Average power is usually rated at 5W per TVS part.)  Clamping at -1V (one diode drop) to +10V would limit TVS power dissipation and internal gate power dissipation.
David Knierim

Offline Weston

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Re: HFSSTC design help and questions
« Reply #5 on: July 26, 2021, 10:15:43 AM »
The FCA35N60 is a super-junction FET, which are typically not good for high frequency resonant applications.

Compared to traditional FETs, the super-junction FET has a more non-linear output capacitance, which leads to excessive voltage peaking. Additionally, the output capacitance is also typically more lossy, which leads to lower efficiency, even with zero voltage switching.


This is going to manifest as a difficulty in getting a reasonable tuning without a large amount of added drain - source capacitance and higher power dissipation even when tuned correctly.

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Re: HFSSTC design help and questions
« Reply #5 on: July 26, 2021, 10:15:43 AM »

 


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