My HFSSTC Driver Board

[曹靖]

I used ECB to create two HFSSTC driver boards~circuit diagrams in my "12MHz HFSSTC" In the post, one is a direct plug-in with a relatively large volume. The other is a chip IC with a reduced volume by half. The input 12V DC is fed to the driver, and the gate voltage of SiCMOS FET can be seen through the oscilloscope image. The input voltage can be further increased to achieve a suitable gate driver. I have used this driver to make various HFSSTCs of 4MHz, 8MHz, and 12MHz. The disadvantage of this driver is that it is difficult to tune. Driving and tuning on 4MHz seems very simple, and it can output 5W to 20W drives The dynamic power driver basically does not generate heat. When the frequency is increased to 12MHz, a small heat sink is needed, and the driving voltage also needs to be increased from 12V to the desired value. This increases the heating capacity of the driving board :'(

[davekni]

The disadvantage of this driver is that it is difficult to tune.

I wonder if tuning would be any easier if GDT windings were interleaved or twisted as in my 13.56MHz version.  2:1 ratio is still possible.  Parallel two wires for secondary so that every primary turn is adjacent one secondary turn.  With primary and secondary turns paired closely together, leakage inductance is lower and controlled mostly by wire length and spacing.  Spacing is usually stable (defined by insulation thickness), especially for twisted pairs.  Core permeability makes much less difference this way.

Even though 2:1 winding ratio is possible with paired wires, I'd recommend trying 1:1 ratio and more turns (3 or more) as in my version.  Voltage ratio can still be 2:1 by having 1:2 capacitance ratio.  In other words, make driver output capacitance (including FET drain capacitance) about 1nF while gate capacitance is about 2nF.  Then adjust GDT wire length (leads + winding) to get 264nH leakage inductance (12MHz resonance with 667pF, which is 1nF in series with 2nF).  Twisted pair wires tend to have about 600 to 660nH per meter, so about 420mm twisted pair length total.

Given your existing available parts, this existing driver may be best option.  Hopefully updated GDT will make it work better.

[曹靖]

I wonder if tuning would be any easier if GDT windings were interleaved or twisted as in my 13.56MHz version.  2:1 ratio is still possible.  Parallel two wires for secondary so that every primary turn is adjacent one secondary turn.  With primary and secondary turns paired closely together, leakage inductance is lower and controlled mostly by wire length and spacing.  Spacing is usually stable (defined by insulation thickness), especially for twisted pairs.  Core permeability makes much less difference this way.

Even though 2:1 winding ratio is possible with paired wires, I'd recommend trying 1:1 ratio and more turns (3 or more) as in my version.  Voltage ratio can still be 2:1 by having 1:2 capacitance ratio.  In other words, make driver output capacitance (including FET drain capacitance) about 1nF while gate capacitance is about 2nF.  Then adjust GDT wire length (leads + winding) to get 264nH leakage inductance (12MHz resonance with 667pF, which is 1nF in series with 2nF).  Twisted pair wires tend to have about 600 to 660nH per meter, so about 420mm twisted pair length total.

Given your existing available parts, this existing driver may be best option.  Hopefully updated GDT will make it work better.

Yes, using a 1:1 GDT would be better, but it needs to be readjusted. Adjusting it can be quite cumbersome. The two GDTs interact with each other (the IRF520 gate GDT in the driver board and the driven NVH4L080N120 gate GDT), so I don't plan to use this driver board anymore. Your driver generates less heat and does not require heat dissipation fins. It is also small and has more advantages than mine

[曹靖]

Update the driver circuit based on https://highvoltageforum.net/index.php?topic=1638.msg12549#msg12549 The circuit is limited by variants with limited materials at hand

[YSPACE Labs]

Instead of a crystal, maybe use a VCO or something. Temperature drift could be an issue with that though (a varactor tuned Colpitts Oscillator may not drift that much). There are also ICs like the Si5351 that can output any frequency set by I2C commands and synthesized from a crystal. But that obviously requires a digital circuit to tune it. Feedback would be the most optimal solution, but that would be very hard at 13.56MHz.

[davekni]

The circuit is limited by variants with limited materials at hand

How is the CD4049 working?  74HC14 is faster and I think a bit higher output drive too.  Is CD4049 supply voltage any higher than 6.5V?  That would be its advantage, ability to handle higher supply voltage.

[曹靖]

How is the CD4049 working?  74HC14 is faster and I think a bit higher output drive too.  Is CD4049 supply voltage any higher than 6.5V?  That would be its advantage, ability to handle higher supply voltage.

There are six NOT gates in CD4049, each of which is a CMOS inverter. The input power supply voltage range is between 3V to 15V, with a maximum of 18V, which can easily drive two TTL loads. I tried to input too high a voltage, which can indeed make the IRF610 obtain higher gate voltage. However, its speed is too slow, resulting in an output waveform like a half sine wave. This is far inferior to 74HC14, but the voltage range of 74 is too small. If there is a chance, I should purchase some faster ICs such as SN74AUC1G74DCTR and SN74AUC2G04DBVR according to your schematic

[NyaaX_X]

Maybe use UCC27525 driving IC ? https://www.ti.com/product/zh-tw/UCC27525 Seems a bits slow ..

[曹靖]

Due to the large internal resistance of IRF610, it may have caused my driver output to be low. Today, I searched through my component box and found FDD8424. Unfortunately, it consists of a device that combines NMOS and PMOS. I checked the information and found that its internal resistance is much smaller than IRF610. The opening voltage is also lower than 610, so I plan to give it a try. I only use its internal NMOS, and I disabled the gate and source short circuits of PMOS. Unfortunately, I found that its Cgs are close to 1nF, which is higher than IRF610 It is many times higher - it may require more driving power to obtain the appropriate gate voltage - but I will try it anyway - indeed, it is - the output is indeed many times stronger than the IRF610- but the internal Cgs are too high, causing insufficient driving and the drain waveform to be unreasonable - but I have achieved the ideal gate voltage on SicFET

[曹靖]

Instead of a crystal, maybe use a VCO or something. Temperature drift could be an issue with that though (a varactor tuned Colpitts Oscillator may not drift that much). There are also ICs like the Si5351 that can output any frequency set by I2C commands and synthesized from a crystal. But that obviously requires a digital circuit to tune it. Feedback would be the most optimal solution, but that would be very hard at 13.56MHz.

The driver with feedback is indeed good, and it may need to increase PLL to track frequency. To achieve this, it may require a lot of experimentation

[曹靖]

Maybe use UCC27525 driving IC ? https://www.ti.com/product/zh-tw/UCC27525 Seems a bits slow ..

Unfortunately, I don't have any of these devices at hand, so I can't actually verify them                   
可惜我手里没有这些元件～所以也没办法实际验证

[davekni]

The driver with feedback is indeed good, and it may need to increase PLL to track frequency. To achieve this, it may require a lot of experimentation

Most HFSSTC circuits use feedback without PLL or gate driver.  Vgs is generated by voltage across a capacitor in series with ground side of primary resonant capacitor (75pF vacuum capacitor).  No active parts in entire circuit except the one power FET.
I built my fixed frequency version to see if such was possible and to run at that ISM frequency where operation would actually comply with EMI regulations.

[曹靖]

Most HFSSTC circuits use feedback without PLL or gate driver.  Vgs is generated by voltage across a capacitor in series with ground side of primary resonant capacitor (75pF vacuum capacitor).  No active parts in entire circuit except the one power FET.
I built my fixed frequency version to see if such was possible and to run at that ISM frequency where operation would actually comply with EMI regulations.

I have also established a similar circuit~add several strontium chloride and sodium chloride breakthrough and schematic diagrams

[davekni]

I have also established a similar circuit~add several strontium chloride and sodium chloride breakthrough and schematic diagrams

Looks good.  Have you tried that with your SiC FET?  Steve Ward used a similar circuit for his 9MHz 3kW SiC FET HFSSTC.  I have not personally made any HFSSTCs with feedback for gate drive.  Only my two fixed frequency coils.

[曹靖]

Looks good.  Have you tried that with your SiC FET?  Steve Ward used a similar circuit for his 9MHz 3kW SiC FET HFSSTC.  I have not personally made any HFSSTCs with feedback for gate drive.  Only my two fixed frequency coils.

At present, I am using ordinary SiFETs for this type of self-excited oscillation HFSSTC. Their performance is similar to that of fixed frequency HFSSTC. The frequency of self-excited oscillation HFSSTC is also very stable. The channel current is also basically constant over a large range. There is an oscilloscope image that shows the Vgs and Vds of self-excited oscillation HFSSTC. I have not yet tried using SiCFET for self-excited oscillation HFSSTC, as I have also established multiple sets of HFSSTC with different fixed frequencies Using SiCFET

[davekni]

Waveforms look great!