Power MOSFETs with fast recovery body diodes

[davekni]

"I did notice reduced performance with less snubbing capacitance with that other driver I've been messing with, it switches much slower anyway but going below 47nF makes the output power diminish. Like the voltage might get a tad higher but it goes really weak and spindly."

Too low a flyback resonant capacitor can make the primary waveform too fast for the secondary to follow, given the secondary's parasitic winding capacitance.  The primary ends up resonating more with the transformer's leakage inductance, with little energy transferring to the secondary.

Glad that LTSpice is working well for you!

[John123]

To be honest I'm finding it a bit hard to understand, I've downloaded the files from Vishays website but can't find a way to actually install them.

The files are downloaded here https://www.vishay.com/mosfets/list/product-92209/tab/designtools-ppg/ but it comes in a .zip form and doesn't make much sense 

I've tried watching a few youtube tutorials but they don't appear to work.

Edit: I think I got it by opening the .lib file in ltspice and right clicking on the .subckt part and creating symbol, then it appears in auto generated when adding a new component. But the symbol looks weird and not like other MOSFETs in the program.

But now the simulations are taking ages to run.

Anyway I was trying to simulate what would happen if the controller IC in the circuit I posted was swapped for the 99% max duty cycle type, is the fet likely to go pop if the snubber hasn't had enough time to do its thing?

[davekni]

Manufacturer-supplied models are often rather complex, making them slow on LTSpice.  The up-side is that such models often include lead inductances and very detailed behavior of parasitic capacitances etc.  But, for most simulations, a basic model is fine and much faster.

LTSpice actually has a unique internal model for power MOSFETs that they call VDMOS.  It's very efficient for simulation and usually good enough for most purposes.  (In certain cases where lead inductance is critical, I add external inductors to simulate that.)  All the FETs in the library file I sent are using that internal model.  LTSpice comes with many included device models as well.  Usually searching down that list will reveal one close enough for basic simulations.  Right-click on the NMOS part in your schematic, select "Pick New MOSFET", then scroll through the list and/or sort by parameter.

There was (and perhaps is) a tool for building VDMOS models.  It lived within yahoo groups, which has gone away.  Hopefully the tool is archived somewhere else.  I have it on my work computer (inaccessible at the moment), and used it to generate all the models in the library file I'd sent you.  If I can find a link to the tool, I'll share it.

[John123]

That would explain it then! I'm just not sure how to add the MOSFET library you sent me, can't quite figure it out (yet).

Back to the circuit for a moment, would switching to the 100% max duty cycle version of the chip likely cause blown silicon? I'm thinking for lower primary voltages like 12v it might help produce more output voltage with some more stubborn flybacks without having to drop the frequency into the hearing range, the simulation would suggest there's more room for play to about 75% but just wanted to be sure before I blow something.

How critical is the off time vs on time?

Edit: Tried a KA3843 and it would appear the 50% duty cycle limit is needed for general purpose use, I was able to crank the power up using the 100% (95% actual) max chip up until a certain point where the output from the flyback would vanish and current draw would remain high. Shame they don't make a chip with a 70% limit as that's where it drops off.

But there was definitely gains to be made across the board, near the hearing range arcs could start at a much larger distance whilst at higher frequencies arcs were thicker and could be stretched out further. Overall the circuit appears to be a lot more noisy and screechy so I'm guessing keeping it below the critical duty cycle operating point is no trivial task with a load such as an arc.

Edit2: Tried another flyback and it appears to have another runaway mode at higher duty cycle setpoints, arcs keep going but the current disproportionately shoots up without having anything to show for it on the output.

Edit3: Tried that useless monitor flyback its just as useless regardless!

[davekni]

John,

First, the simulation file has a line ".inc fet.lib" on the schematic.  As long as the file "fet.lib" is in the same directory as the circuit, it will be read in.  (A full path can be used for the ".inc" command.)

There may be more GUI methods to select parts from a user library, but I use the crude text options.  Either right-click on the part-name text of the FET, or cntl-right-click on the FET symbol body.  Then type in one of the parts in the library.  (I edit the fet.lib file using a text editor, but I gather you can do that within LTSpice.)

For normal flyback operation (not drawing arcs), the necessary minimum off-time is the half-cycle time of the primary LC resonance (transformer primary L and resonant C, 100nF in your case).  For TVs, this is usually 10-20% of the period (80-90% on-time).  The minimum off-time is a fixed time value (defined by L and C), not a fixed duty-cycle value.  Minimum off-time of KA3843 is determined by oscillator capacitor value and internal pull-down current.  See figure 6 in the spec.  If you pick a capacitor to get the correct off-time (dead-time) for a given flyback and resonant capacitor, you can adjust frequency by changing the oscillator R.  The R value has little effect on dead-time.  (Can you scope the flyback primary to see the resonant half-cycle time?)

When drawing arcs, the waveform gets messy, some combination of the normal resonance and the higher-frequency resonance of flyback leakage inductance.  The above dead-time may still work reasonably well.  A fancier option would be to detect the voltage across the resonant capacitor, and extend the dead-time until resonant capacitor voltage is back close to zero.

Yes, too short a dead-time is likely to fry the FET, as the FET is discharging the resonant cap directly, resulting in very-high inrush current.

Monitor flybacks typically run at much higher frequencies, which makes handling secondary winding capacitance tricky.  My guess is that such flybacks are carefully tuned for a specific resonant capacitance and frequency that works will with the secondary resonances.

[John123]

For some reason the power adjust pot allows the duty cycle to go all the way down to 0% without altering the timing cap, I'm not quite sure how it works but I think it lowers the maximum allowable peak current across the sense resistor.

I might be able to scope the drain whilst running at lower powers, I've only got a x10 300v probe so don't want to risk damaging the scope. My worry is at startup there could be tranistants exceeding this.

I've been reading online and found I might need something called slope compensation to make it more stable at >50% duty cycles, not sure if that's suited to the current schematic however. One method used a resistor from the timing cap to current sense pin whilst another used a signal transistor along with the resistor. Another said to put a signal diode between the gate drive output to current sensing pin.

[davekni]

John,

Looking KA3843 spec. figure 6, the 3.3nF on KA3843-4 in the schematic you shared would result in a bit less than 1us dead-time, which may appear as roughly 0.  (I'm presuming you meant all the way to 0% dead time, not 0% duty cycle.)  The flyback half-cycle time is likely around 10us, which requires 47nF from pin 4 to ground.  The 22k POT will need to drop to 1-2k to get reasonable frequency range with 47nF.

At higher frequencies (low POT values), the dead-time will increase some even with a constant capacitor value, as the POT's pull-up current is competing with the KA3843's internal 6.3mA pull-down current.

For this flyback use, I don't think slope compensation is needed.  Slope compensation is needed for continuous current-mode switchers, where the current increases during the on-time and decreases during the off-time, but not to zero.  In this situation, slope-compensation avoids sub-harmonic oscillations (on-time varying in a cyclic pattern over many cycles).  The biggest issue with sub-harmonic oscillations is audible noise, not parts frying.

For probing, yes, 300V may not be enough probe capability.  One easy solution in this case is to lay the probe near the FET drain but not touching, or wrap a small bit of insulated wire around the probe end and connect that wire to the drain.  This gets enough of the AC signal to see the flyback half-cycle time.  The only trick here will be keeping the flyback secondary far enough away to not couple to the probe much.  A simple grounded shield, such as a grounded piece of sheet-metal or foil, propped roughly at the flyback transformer is likely enough to separate primary and secondary electrostatic fields.

[SteveN87]

If you want to do lots of measurements, it might be worth turning your resonant capacitor (100nF?) into a capacitive voltage divider. E.g. adding 1uF in series at the bottom end gets you a x11 probe point. The total capacitance will be a little lower at 91nF.