General sstc questions ssts 5 built

[niels]

Hi Guys,

Because of your recomendations I built steve wards ssts 5 and while Troubleshooting some questions raised which I couldn’t answer myself. Before I connect anything I wanted the gate signal to get right so I feed the diver with my signal generator, disconnected the 555 timer and connected the gtd and the mosfet but with no power connected to the halfbrige  the signal looked not too bad or is this signal not suited




 but at this point I already made three gtds as the results of the first tow locked horrible. In the first picture I set the signal generator at 100khz and a square wave. when I set it to sine the output looks really weird which made me wonder because the signal which gest eventually picked up by the antenna should look more like a sine wave. In another post I read that tying the unused inputsof the 74h14 with a resistor to ground could help which it unfortunately didn’t. Can you think of a reason why this is or is this signal with the sine wave as an input good enough for the ucc (already tried changing the chip with no success)




After then connecting it to the power supply (input again on square wave) the power consumption increased rapidly. It reached the set current limit of 0.8 amps for testing at about 12 volts.




 This behavior made me believe that the mosfets are shorting the power supply as the upper one gets slightly warm. Now the question is what the reasons for a shoot trough are. I checked if the mosfets don’t switch at the same time, which they didn’t. also, the ucc were not getting warm which excludes that they are too weak to charge and discharge the mosfets quick enough or am I wrong there? I Also tried switching the mosfets to fresh ones. The only other reason that came to my mind was that the uccs switch the mosfets not too accurate so there is a very short overlap (the ucc are fine I changed them already). After doing a bit of research I found a highside-lowside mosfet driver chip from Texas instruments the ucc27714. A brief look in the datasheet tells me that it has a specific dead time. I thought that the dead time could only be beneficial for a tesla coil or am I wrong? Another benefit of this chip is that it would eliminate the need of a gtd. I found that getting the gtd right is pretty hard to achieve so eliminating it would also eliminate another point of failure. As I’m pretty new to tesla coils, I wonder whether this chip is even suited for one so I wanted to ask if anyone has experience with it. Unfortunately trying it out is quite difficult because it would require an pcb as it only comes in a smd package that’s why I wanted an opinion of someone who knows this topic a bit better than me.
While playing with different circuits I realized that often some high frequency noise at the gate is implemented and I asked myself where does it come from and why isn’t it common practice to install a lowpass filter at the gate of the mosfet tuned to right abof the resonant frequency of the coil.

[davekni]

Pictures of your build showing wiring and GDT would help, and information on what core you used for the GDT.

What sine-wave voltage was your signal generator producing?  Was the signal generator ground connected to the driver circuit ground?  For this circuit, it is best to add some resistance (say 1k ohm) between the signal generator output and the antenna input.  Otherwise, if the generator is producing more than 6Vpp, the input clamp diodes D7 and D8 may conduct high current.  (If the generator is putting out much less than 6Vpp, then the HC14 input doesn't have a defined DC level, so that could explain your erratic gate waveforms.)

Yes, there are issues with the waveforms.  Most likely cause is parasitic inductance of wiring - why pictures are helpful.

Yes, unused logic chip inputs should be tied to a stable voltage, either 0 or +5v.  Resistor is not necessary.  They can be tied in a chain, such as pin 13 to 14, 11 to 12, 9 to 10.

[niels]

Thanks for the fast answer!

I used a core with an AL of 1275 nH it was advertised to work up to 50Mhz so I thought it would be good enough.
Firstly I tried to wound it with single wires After seeing that it doesn't work I used the shielding of a coax wire as the primary and two twisted wires of an old network kable inside the coax as the secondary. Is there rule of thumb What reduces or increases Parasitic inductance?

I put the output of the generator as low as possible but still working at 4 Vpp any lower than that and the output is just nonsense. For test purposes with the signal generator I removed the diodes d7 and d8 as the voltage wouldn't exceed the maximum input voltage of the chip.
(the mostest will get proper cooling once I connect It to the coil)

[davekni]

Your GDT using twisted pair inside coax is great.  To keep its nice low leakage inductance, wiring to and from the GDT needs to be paired too.  (White wires twisted together, orange wires twisted together, and green wires twisted together.)

Most designs separate the driver and half-bridge (power FETs) onto two separate boards.  That helps keep the high-voltage high-current switching spikes away from sensitive control circuitry.  The half-bridge itself needs much lower wiring inductance.  Here's an example I posted for low-inductance half-bridge layout:
https://highvoltageforum.net/index.php?topic=1324.msg9795#msg9795

I suggest keeping your driver as-built, and constructing a new half-bridge layout using copper planes (either foil or copper-clad).

Finally, the gate series resistors look to be wire-wound.  That adds more excess inductance.  Carbon composition or metal oxide gate resistors are great.  Metal film or carbon film can work if power dissipation isn't too high.

[niels]

Thanks for the Help,

I Built the half bridge exactly the way as you did But it didn't work out.It behaved exactly as before. there are no shorts once it is turned of also the phasing of the gates is right

After trying it out once I think the driver died as there was no more output signal although it died silently without any smoke. I think the large voltage spikes where the reason why it died. I don't have any drivers left so I don't have a Photo of the gate voltage before I died. I have no Idea why it behaves like this. I read that it is possible to implement an Inductor at the Gate to Devine a specific dead time could this exclude the possibility of cross conduction?

[davekni]

Mostly a nice copy of my copper plane layout!  However, there is one critical error that is frying drivers.  Your high-side GDT connection is to the FET drain (VBus+).  Both GDT secondaries must return to their respective FET source pins.  (Your low-side GDT returns to source as Steve's SSTC5 schematic shows.)  Looking back at your original build, it appears to have the same error.

A more minor detail:  It is better to have the GDT secondary windings return to the FET source pins close to the FET package bodies, not to the power planes.  That way less of the FET lead inductance is included in the gate circuit.  The high switching source-to-drain currents cause voltage spikes across lead inductance.  It's best to keep such spikes out of gate waveforms.

With a new driver chip and the above fixed, you should have much better luck.