SSTC - PCB design

[Przemekk00]

Hi,
Recently i decided to give another try and build Mads's SSTC 2. Last time i had problems with proper working at voltages higher than 130VDC (transistors were being destroyed due to crossconduction or gate voltage spikes, hard to say). Reducing bridge leakage inductance and adding snubber capacitor gave some positive results - it was able to work at around 220VDC, but it's still long way to rectified mains voltage (320V). This time i decided to make it look more professional and design a PCB and since it's my first circuit layout with use of computer software I want to get some opinions about my design, and what should I change if it's necessary.

Photos: https://mega.nz/folder/VqJDmSxI#ZC-xRg52OImkEYI395y0Vw

[davekni]

Generally looks good.  Nice use of copper planes!

I'd recommend that every IC have at least one bypass capacitor on its supply pin.  For the high-current UCC driver chips, two caps is recommended, one for each VDD pin (pin 1 and pin .

Great work on your first ECB!

[Mads Barnkob]

Use of two sided board and parallel DC bus planes on the power section is already super great!

You could take a look at the similar DRSSTC driver PCB designs, which are free and open to all, get some inspiration here: https://highvoltageforum.net/index.php?topic=353.0

I got a few comments:
Green boxes: Your power traces got components too far from each other, minimize your circuit paths in high current circuits.
Blue box: The respect distance between potentials and legs are too small, for no reason, you got plenty of space to make it larger. Switching transients and being in a high voltage EMF, makes a Tesla coil circuit more exposed to such failures.
Gray box: Components are too spread out and track lines are too thin, for no reason.

Make room or rotate your voltage regulators, to have a heat sink mounted.
Do not have electrolytic capacitors too near to heat sources.

Aesthetically I only use 45 degree bends on tracks, no Y forks or 90 degree bends around pins. But that is not important

[Przemekk00]

I added a few bypass capacitors, made tracks thicker, decreased distance between componets and changed footprint of GDT - mosfet gate connections. New screenshots are labeled as v2 in same mega.nz folder.

[davekni]

I added a few bypass capacitors, made tracks thicker, decreased distance between componets and changed footprint of GDT - mosfet gate connections. New screenshots are labeled as v2 in same mega.nz folder.

Good improvements.  A couple more suggestions:
Bypass capacitors are placed well for U3, U4, and U5, adjacent power pin.  U2 and U6 would be better with bypass capacitors moved to adjacent their power pins.  Also, traces from power pins to bypass capacitors should be wide to minimize inductance.
I think Mads suggestion is to increase gaps between traces and planes in the power section.  That is probably a global parameter or a parameter on each of the plane rectangles, what space to provide around pins and traces.  I worry less about that than Mads does since this is only 320V and using 500V FETs.  Spikes much above 500V will be clamped by FET avalanche breakdown (or damage the FET if long enough) rather than cause arcing on the ECB.  However, some increase in clearance distance would be a good idea to make sure.

[Przemekk00]

Thank you for your help, beside circuit layout I increased gate resistance to 15 ohms to supress oscilations in exchange for rise and fall time. I also added a ferrite bead (RRH-40-20-100) to every transistor. Turns out it was enough and coil works properly at 320V DC.