IGBT lead inductance and turn-off voltage spikes

[davekni]

Made a test circuit to measure IGBT turn-off characteristics at relatively high current as is needed for phase-shift QCW use.  Made with copper foil on both sides of 1mm plastic (polycarbonate) to minimize interconnect inductance.  IGBT leads are held against copper with a spring clamp and rubber pad to allow for replacing parts.  Thermocouple taped and clamped to IGBT top, also clamping IGBT to a small piece of aluminum sheet metal to simulate heat sink.  Having that heat sink metal adjacent and parallel to circuit board helps reduce inductance.  IGBT body is against edge of circuit board (foil/plastic) for almost zero (<1mm) external lead length.  Still some lead length inside package epoxy.  This testing is at 320Vbus, switching from 140A to 0A.

Schematic:



Picture with spring clamp holding IGBT leads.  Only connection between left emitter lead carrying 140A and right emitter lead for gate drive is inside IGBT package.  Isolated on board.  Gate drive is from GDT through buffer, so circuitry is isolated too.



Spring clamp removed for visibility:



Even with all the measures to minimize parasitic inductance, voltage spikes are high.  These are fast IGBTs, chosen intentionally for phase-shift QCW, to minimize turn-off energy.  First scope plot (left image) shows Vge with ~12ns fall time and Vee (voltage from one emitter lead to the other).  Emitter spike is ~55V and around 12ns wide, indicating roughly 12ns current fall time.  Shows value of Kelvin connection (of not adding that 55V signal to internal gate voltage).  Also shows how spike exists just across internal-package lead inductance.  Right plot shows Vce, measured on board foil and again on IGBT package back-side (on heat sink aluminum).  About 50V difference.  Combined emitter and collector spikes add 105V to internal IGBT Vce due to just inductance of leads inside package.
Red is Vge and blue is Vee on left plot.  Green is measuring current.  Ignore that one for turn-off.  Inductance in current-sense resistors causes large spike compared to the 28V drop at 140A.  Right plot, red is Vce measured on IGBT package back (heat sink).  Blue is Vce measured on board foil.



Next scope plot shows Vge with ~12ns fall time, and again at ~30ns fall time in the hopes that current fall time might increase a bit.  Delays Vce spike (measured on foil), but doesn't reduce amplitude significantly:



Tried 50ns Vge fall time.  Still no reduction in spikes.  Current fall is enough delayed from Vge fall that Vge timing doesn't seem to matter.



Tried even slower, 120ns Vge fall time.  Still same spike amplitude.  (Horizontal scale is now 25ns/div, so spike looks narrower.  Really about the same.)  Blue is Vge.  Red is Vce measured on board foil.



Fast switching is good for low Eoff.  Was hoping to slow it slightly.  Looks like I'll need some R+C snubbers instead to keep Vce below 650V specification.  BTW, I fried first test part testing at 200A before realizing how high spikes were.  Even at 140A, considering combined emitter and collector spikes, peak voltage is about 700V, so slightly above spec limit.  LTSpice simulations appear to show R+C snubbing will be effective.  Adds significant power dissipation.  However, at least that power is in resistors, so not adding to thermal stress of IGBT die.

[alan sailer]

That a great piece of engineering. Did you try and move the IGBJT further from the circuit to watch the expected increase in the overshoot? Or is that
so guaranteed it's not worth doing?

I'd be curious about your snubber design. The phase shift QCW I built had awesome spikes on the hard switched side of the bridge and I never had the guts to run it all full doubled voltage. If I could just kill some of the spike amplitude I'd be motivated to revisit the beast.

Cheers.

[davekni]

Did you try and move the IGBJT further from the circuit to watch the expected increase in the overshoot?

That is a good idea.  Made this test to match my design techniques.  That makes it less useful for everyone.  However, to run with longer leads requires testing at lower current and/or voltage.  Above test indicates peak of 700Vce internal to IGBT die.  These IGBTs are specified for 650Vce maximum.  They have no avalanche energy specification, so likely not designed to handle avalanche breakdown.  (Avalanche breakdown may be localized, not spread out enough across die to absorb significant energy.)  I already fried one part testing at higher current.  Repeating existing test at lower voltage and current, then with longer leads, will allow comparison.  Perhaps I'll get to a quick run of that next weekend.

Continued testing at 320Vbus and 140A:

Next step was to test with 10 ohms in series with gate after source-follower buffer.  Previous slower Vge fall time were done by slowing down ramp rate before source-follower buffer feeding IGBT.  Gate series resistor produces expected Miller plateau and somewhat lower peak Vce.  One feature of gate resistors and Miller plateau is that Vce slew rate is slowed greatly at the beginning of its rising edge and much less so at the end.  That is because Ccg is much higher at low Vce than at high Vce.  Left scope capture below shows Vge in red and Vce in blue.  Right plot shows same Vce, both at 100V/div and at 10V/div to see the slow initial Vce rise.  Here Vce is measured on copper foil, so does not include IGBT internal lead inductance on collector or emitter.



Final experiment was adding Vce R+C snubber, testing what I plan to add to my QCW H-bridge from this thread:
    https://highvoltageforum.net/index.php?topic=2397.msg17600#msg17600
Per simulation, snubber is 11nF in series with 1.2ohms for each IGBT pair (22nF + 0.6 ohms for each half-bridge since I have two parallel IGBTs for each switch).  I've ordered some 2512 2W pulse-rated resistors for my QCW H-bridge.  For this test, used what I had around.  Initial test used 4 parallel 4.7ohm 0.5W thin-film 1206 resistors.  Thought that would be enough for this low-frequency testing.  At 20Hz rate, resistors fried open after a few seconds.  Replaced with 8 parallel 10ohm 0.25W 1206 thick-film resistors.  Those lasted for my 20Hz testing to capture scope images.  After 1kHz testing for thermal measurement (more down below), no resistor completely failed, but net resistance increased from 1.25ohms to 1.9ohms.

Edit:  Removed resistors for next test.  Individual 10-ohm resistors measured from 13ohms to 20ohms.

Left plot below is Vge in red and Vce in blue (measured on copper plane).  Right plot is Vce, blue measured on copper plane and red measured on IGBT case back-side to include collector lead inductance.  At first glance they look surprisingly similar.  However, voltage delta is relatively high (just over 50V) early during Vce rise, about the same as without snubber.  Difference is that this inductive spike does not add to peak voltage.  Inductive spike occurs when current drops.  Snubber slows Vce rise so that external Vce is still low during inductive spike.



Below is measurement of voltage between emitter lead for Vge and emitter lead for Vce in red at 5V/div and Vce at 100V/div in blue.  As with collector lead inductance, emitter spike is early when current drops before Vce is very high, so does not add to peak Vce of IGBT die.



I'm not certain what causes the second smaller Vee spike.  Vce rate-of-rise does appear to increase a bit at that time, suggesting a final drop in IGBT current, consistent with a Vee spike.  Not sure why IGBT current appears to decrease most of the way (perhaps 100% to 10%) then later suddenly drop the remaining bit.  Perhaps if this IGBT is built with trenches, there is a difference in turn-off time of vertical and horizontal portions of channel.  Anyone have possibilities to suggest?

Final test (so far) was to measure Eoff (IGBT turn-off energy) by comparing temperature rise of IGBT under 1kHz testing and compare with DC power dissipation at known voltage and current.  Not super-accurate data since my test setup was limited to roughly 1kHz.  Eoff for three cases:
    1.45mJ for initial test with fast Vge fall and no series resistor.
    1.7mJ for 10-ohm gate series resistor.
    1.35mJ for fast Vge fall and snubber on Vce.  This does not include snubber power dissipation.
If snubber power is included, 10 ohm gate resistor is likely more efficient.  However, for my phase-shift QCW, IGBT power is more important than total power.  Transient thermal impedance of IGBT will barely allow 1.35mJ.  Snubber also lowers peak IGBT voltage better, so allow more margin to increase Vbus, allowing more stored energy to feed each burst.

[davekni]

Did you try and move the IGBJT further from the circuit to watch the expected increase in the overshoot?

That is a good idea.  Made this test to match my design techniques.  That makes it less useful for everyone.  However, to run with longer leads requires testing at lower current and/or voltage.  Above test indicates peak of 700Vce internal to IGBT die.  These IGBTs are specified for 650Vce maximum.  They have no avalanche energy specification, so likely not designed to handle avalanche breakdown.  (Avalanche breakdown may be localized, not spread out enough across die to absorb significant energy.)  I already fried one part testing at higher current.  Repeating existing test at lower voltage and current, then with longer leads, will allow comparison.  Perhaps I'll get to a quick run of that next weekend.

Made a quick test at lower current and voltage (80A 180Vbus) to compare existing ~1mm gap from package to copper and a more common 6mm gap.  This isn't completely representative of normal H-bridges, however.  In this test setup, diodes are soldered to copper foil and in series with current sense resistors.  Inductance of diodes+resistors does not change, so spike voltage as measured on copper foil does not change significantly.  In a normal H-bridge, diode(s) are within opposite-side IGBT.  Increased lead length for that opposite IGBT would further increase resulting Vce spike.  Where change does show up here is between IGBT leads and internal IGBT voltage as measured on back case for collector and kelvin emitter connection.  Images of IGBT at 1mm and 6mm from copper:



Resulting scope measurements:  Blue traces are from IGBT at 1mm, red with IGBT at 6mm.  Left plot is Vce measured on copper foil.  Little change.  Middle plot is Vce measured on IGBT case (relative to emitter on copper foil).  Additional ~40V spike amplitude across the additional 5mm lead length.  Right plot is emitter to emitter, about 17V additional spike across additional 5mm lead length.  However, the actual increase may be higher.  The two emitter leads are adjacent, so have significant mutual inductance.  Some of the high-current emitter lead voltage is induced on the adjacent gate-return emitter lead, so subtracted from what is measured between the two leads.



Differences would be ~75% higher at the previous test conditions of 140A compared to this 80A test.

[alan sailer]

David,

That is really good. I don't have any real experience with lead inductance caused spikes. I've always just believed more experienced coil builders when they say keep the lead inductance as low as possible.

I understand the mechanism behind the spikes but it has always seemed intuitively weird that such a minor length of wire can kill devices. Thanks for showing the real data.

Cheers.