Half-bridge for my first sstc

[LoOdaK]

Hi all, as I said a couple of months ago I started to build my first SSTC.
Because I'm quite new to this, I tried to design a PCB for the half-bridge. I was mainly following schematics from the Internet.

I would like to hear your opinions, there are probably thousands of mistakes and that is why I'm posting it here
What could be improved ? What are my mistakes, and how I can fix them ? What to look out for when designing this kind of board ?

Schematic: (Sorry for the template, still working on it )





Top layer:


Bottom layer:


Both layers:



Final look:

[Mads Barnkob]

Keep your power traces as short as possible, you did that, fine layout.

I avoid 90 degree edges, I make them all 45 degree. Sharps edges and high frequency high voltage is just an unnecessary risk, as you can have high voltage transients or resonant voltages in Tesla coil inverters.

Your power traces are VERY close to each other, you have plenty of space on the board, give them some more spacing, same reason as above, switching transients can quickly cause a flashover that turns into a board fire because the distance is so small that an electrical arc can sustain.

[davekni]

Your schematic lists 1N4148 diodes.  Peak current is likely to exceed rated 0.5A.  I'd suggest 1N5817/8/9 instead.

BTW, for TC frequencies, inside copper corners aren't an issue.  Outside corners are the key concern for HV.  (Rounded inside corners can reduce trace cracking with bending stress, so wouldn't hurt.)

Your overlapping shapes for VDC and GND are great.  Keeps parasitic inductance low.

[LoOdaK]

Keep your power traces as short as possible, you did that, fine layout.

I avoid 90 degree edges, I make them all 45 degree. Sharps edges and high frequency high voltage is just an unnecessary risk, as you can have high voltage transients or resonant voltages in Tesla coil inverters.

Your power traces are VERY close to each other, you have plenty of space on the board, give them some more spacing, same reason as above, switching transients can quickly cause a flashover that turns into a board fire because the distance is so small that an electrical arc can sustain.

Thanks a lot for the info.
Yes, my traces are quite close to each other, I'm working on it but I don't want to extend traces too much because I want to lower parasitic inductance.

Your schematic lists 1N4148 diodes.  Peak current is likely to exceed rated 0.5A.  I'd suggest 1N5817/8/9 instead.

BTW, for TC frequencies, inside copper corners aren't an issue.  Outside corners are the key concern for HV.  (Rounded inside corners can reduce trace cracking with bending stress, so wouldn't hurt.)

Your overlapping shapes for VDC and GND are great.  Keeps parasitic inductance low.

Thanks for the 1n4148 info, I will consider replacing it.

I'm not quite sure what do you mean by inside/outside copper corners, how that could be fixed on my board ?

Concerning overlapping shapes, would it help if I remove the copper area above capacitor terminals that go to the edge of the board to lower parasitic inductance even more ?

[klugesmith]

Very pretty. I might even ask if I can sign up to get one of those boards.

I don't see any connectors or open vias for bringing in VDC and GND.   
How and where will you attach those wires?

[davekni]

I'm not quite sure what do you mean by inside/outside copper corners, how that could be fixed on my board ?

By inside corner I refer to concave corners of a copper shape.  By outside corners I refer to convex corners.

Concerning overlapping shapes, would it help if I remove the copper area above capacitor terminals that go to the edge of the board to lower parasitic inductance even more ?

I was complimenting you on a good layout, not recommending any changes for reduced inductance.  No, removing copper never reduces inductance.  Only reason to remove copper is to increase clearance distance as Mads recommended (and I agree).

Yes, my traces are quite close to each other, I'm working on it but I don't want to extend traces too much because I want to lower parasitic inductance.

Yes, increasing spacing does increase inductance.  I'd still increase spacing some.  Especially the gate traces can easily be moved farther from drain without any significant inductance change.  For minimizing inductance, it is more important to have copper on the opposite side of the board from traces than is the exact trace spacing.  You could extend the copper shapes for VDC and GND below the bulk cap to fill in much of the empty area, especially extend the VDC top-layer shape to go around the small cap terminals and over the output trace.  That will reduce inductance more than any increase you get from widening spaces around FET/IGBT leads.

[LoOdaK]

Very pretty. I might even ask if I can sign up to get one of those boards.

I don't see any connectors or open vias for bringing in VDC and GND.   
How and where will you attach those wires?

Thanks a lot, but this is not tested yet.
I wanted to hear from more experienced people in the field about things that could be improved so that's why I posted here.
If the project turns out ok and if everything works as expected, I will happily share my boards here on the forum.
(If you want this unfinished board, PM me, and I will send it)

As for the connections, my plan is to use a screw terminal type capacitor and by using washers and crimp connectors, connect wires directly to the bottom of the PCB.
That's my plan, but I will see if it's viable.

I was complimenting you on a good layout, not recommending any changes for reduced inductance.  No, removing copper never reduces inductance.  Only reason to remove copper is to increase clearance distance as Mads recommended (and I agree).

Yes, increasing spacing does increase inductance.  I'd still increase spacing some.  Especially the gate traces can easily be moved farther from drain without any significant inductance change.  For minimizing inductance, it is more important to have copper on the opposite side of the board from traces than is the exact trace spacing.  You could extend the copper shapes for VDC and GND below the bulk cap to fill in much of the empty area, especially extend the VDC top-layer shape to go around the small cap terminals and over the output trace.  That will reduce inductance more than any increase you get from widening spaces around FET/IGBT leads.

So that means it is actually better to fill as much PCB area as possible with copper on both sides and avoid only gate circuitry ? Did I get that right ?

Is this better layout then previous photo ?

[davekni]

So that means it is actually better to fill as much PCB area as possible with copper on both sides and avoid only gate circuitry ? Did I get that right ?

Is this better layout then previous photo ?

Yes, parasitic inductance is lower in the new version.

Looks like there's still small gaps that risk arcing.  For use at 340Vdc or under (400V FETs), arcing is unlikely even with close spacing.  However, I still recommend as Mads did that you increase spacing.  The copper shapes likely have clearance distance properties that can be increased to automatically make larger clearances from other copper.  Hopefully that will fix tight spacing just above FET/IGBT pads and around capacitor pads.  Output trace width is great in this new layout, but gets a bit close to D1 pads.  If you move the diode pads/holes farther apart, it would accommodate 1N5817/8/9 diodes as an option and clear the output trace better.

BTW, spacing in the lower left and right is fine.  Gate voltages are low and not close to any other voltages there.

[LoOdaK]

So that means it is actually better to fill as much PCB area as possible with copper on both sides and avoid only gate circuitry ? Did I get that right ?

Is this better layout then previous photo ?

Yes, parasitic inductance is lower in the new version.

Looks like there's still small gaps that risk arcing.  For use at 340Vdc or under (400V FETs), arcing is unlikely even with close spacing.  However, I still recommend as Mads did that you increase spacing.  The copper shapes likely have clearance distance properties that can be increased to automatically make larger clearances from other copper.  Hopefully that will fix tight spacing just above FET/IGBT pads and around capacitor pads.  Output trace width is great in this new layout, but gets a bit close to D1 pads.  If you move the diode pads/holes farther apart, it would accommodate 1N5817/8/9 diodes as an option and clear the output trace better.

BTW, spacing in the lower left and right is fine.  Gate voltages are low and not close to any other voltages there.

Thanks a lot.
What do you think now ?
I tried to make some clearances, only thing that bothers me is that JST connectors are not aligned horizontally to each other and it drives me a little bit crazy 

(edit: without f. fab layer)

[davekni]

What do you think now ?
I tried to make some clearances, only thing that bothers me is that JST connectors are not aligned horizontally to each other and it drives me a little bit crazy 

Looking better!  Still some clearances to fix:  Top side of source/emitter of left FET/IGBT, and around hole pads for C1, C2, and C4.
You could lower J1 to match J2 if that makes you feel better   Shouldn't affect functionality.

[LoOdaK]

I did some more clearance adjustments, aligned JST connectors (I hope this won't cause problems), and made adjustments on silkscreen layer.

[davekni]

It looks good to me.  For your voltages, should be fine, unless I'm not noticing something.  If you want to be a perfectionist, you could round the outside corners at the bottom of the left source/emitter trace and the right drain/collector trace.  Either round the traces or pull them up a bit so the rounded pad shape forms the end of the copper.

[LoOdaK]

It looks good to me.  For your voltages, should be fine, unless I'm not noticing something.  If you want to be a perfectionist, you could round the outside corners at the bottom of the left source/emitter trace and the right drain/collector trace.  Either round the traces or pull them up a bit so the rounded pad shape forms the end of the copper.

I rounded them a little bit. Let's hope everything will work fine 
I also exposed copper on the traces from L1A & L1B so I could hopefully reinforce them with some solder. Would that cause any problems ?

Thank you and Mads for those excellent tips. This means a lot to me especially because this is quite new for me. I will have to make some more adjustments for capacitor terminals and will order the board. If everything turns out ok, I will post my results here on the forum.

[davekni]

I also exposed copper on the traces from L1A & L1B so I could hopefully reinforce them with some solder. Would that cause any problems ?

Solder mask does help prevent arcs starting from creepage current.  You have enough clearance distance now that solder mask over those traces shouldn't be needed.
However, I recommend against adding solder.  For typical TC frequencies, adding solder may increase resistance due to skin effect.

[LoOdaK]

I also exposed copper on the traces from L1A & L1B so I could hopefully reinforce them with some solder. Would that cause any problems ?

Solder mask does help prevent arcs starting from creepage current.  You have enough clearance distance now that solder mask over those traces shouldn't be needed.
However, I recommend against adding solder.  For typical TC frequencies, adding solder may increase resistance due to skin effect.

I wanted to increase the current handling capability of the traces but it seems  that would only worsen it. Thanks again.

[davekni]

I wanted to increase the current handling capability of the traces but it seems  that would only worsen it. Thanks again.

Yes, depending on frequency, could make current capability worse or have little effect.  Your trace is likely fine as is.  If you want higher current capability, widen the trace where ever width isn't constrained by nearby pads or traces.  If you really need to augment beyond that, use copper foil tape soldered at the endpoints.

[LoOdaK]

I wanted to increase the current handling capability of the traces but it seems  that would only worsen it. Thanks again.

Yes, depending on frequency, could make current capability worse or have little effect.  Your trace is likely fine as is.  If you want higher current capability, widen the trace where ever width isn't constrained by nearby pads or traces.  If you really need to augment beyond that, use copper foil tape soldered at the endpoints.

Sorry for the late response, thanks again, I will leave it as is (without copper exposed) I hope it will work well.