Author Topic: Gate waveform question  (Read 529 times)

Offline flyingperson23

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Gate waveform question
« on: July 23, 2022, 07:49:57 PM »
Hey, I have my bridge assembled. I did a low bus voltage test and got the attached waveform across the igbt gates. Is there something wrong with this? If so, any ideas on how to fix it?

Offline Mike

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Re: Gate waveform question
« Reply #1 on: July 24, 2022, 01:44:37 AM »
Something is very wrong but I'm struggling to figure out what. Your scope is showing peaks of more than 40V on the gate (if it's set up correctly) which is way too high. Also the duty cycle is very low, it should be 50%. You're zoomed out in time way too far to see what's actually going on, you should be looking at a time scale comparable to the period of your primary oscillation frequency, I'm not sure what that is for your coil, but probably closer to 10us/div.

Finally, what's your test set up? Is it low voltage on your full coil and driver, or are you just testing the bridge with a function generator?

Mike

Offline AstRii

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Re: Gate waveform question
« Reply #2 on: July 24, 2022, 02:41:42 AM »
When you say you tested the bridge, may we know how? Did you applied low voltage to the bus and tested it with a load? If so, can you measure the output of the bridge?
This waveform is absolutely wrong, but if the bridge "works" it may be a broken probe or disconnected ground.
Marek Novotny
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Offline davekni

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Re: Gate waveform question
« Reply #3 on: July 24, 2022, 04:15:16 AM »
I'm guessing that the 750Hz repeat rate is your interrupter frequency.  Recommend testing at much lower interrupter frequency (ideally 1-10Hz) to minimize chances of frying circuitry.  Also start with short interrupter pulse widths, a few cycles worth, for the same reason.  Once things are working correctly, increase duty cycle.

Until gate waveforms and bridge output waveforms look correct, I suggest continuing with signal-generator replacing feedback CT input.  Your scope includes signal generator capability.  I have the same model.  A bit of a pain to use while scoping too, but possible.  Or stay with your external one.  Either way, duty cycle needs to be closer to 50% than in your previous signal-generator waveforms.  Low duty cycle is likely due to low signal-generator output amplitude.  Higher may not be possible with either signal generator.  To work at low amplitudes, change to square-wave output.  Doesn't match real CT signal, but should provide 50% duty cycle.  Square wave is fine (except for adjusting phase lead, which is better to do later with real CT feedback).

Thank you for posting waveforms.  As has been mentioned, more information helps.  State explicitly where scope is connected (ie. ground clip to low-side emitter and probe to gate), what supply is feeding H-bridge (ie. 12V from a bench supply or ...), etc.  Pictures of your build also help, especially if pictures show probe connection(s).  For signals such as in this post, multiple scope captures at different horizontal time/division are needed in order to interpret.  One as shown with several interrupt pulses, and at least one more covering the enable duration of a single interrupt pulse.  If looking at switching glitches, yet another zoomed in to show the glitch or ring of concern.
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Offline flyingperson23

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Re: Gate waveform question
« Reply #4 on: July 25, 2022, 05:18:07 PM »
I have a full bridge of cm300s, which I'm feeding low voltage and getting an output of a few dozen amps. Attached are a few pictures of my setup. Measuring one of the transistors with the emitter at scope ground gets me the attached waveforms. It looks decent and is interrupting at the ~80khz that I'm putting in as a feedback signal, but there are still pretty high voltage spikes and I don't know if that's the general shape it's supposed to take.

Offline flyingperson23

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Re: Gate waveform question
« Reply #5 on: July 26, 2022, 01:46:12 AM »
I realized I should probably disconnect the gdt from the gate before measuring the output - after doing that I got these relatively clean square waves - do they look good?

Offline Mike

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Re: Gate waveform question
« Reply #6 on: July 26, 2022, 03:10:06 AM »
GDT waveforms look good.

The overshoot that you're seeing on the gate is probably the inductance of the leads from the CT resonating with the gate capacitance of your IGBTs. Gate capacitance is fixed, you can't do much about that, so anything you can do to reduce the GDT output inductance (shorten the wires, ensure all leads are tightly twisted, etc) will help. It also looks like you're using a 0.1R gate resistor, I'm not an expert on these larger brick IGBTs at all but would have expected this to be closer to 10R. The gate resistor will damp the ringing during turn on at least.

Mike

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Re: Gate waveform question
« Reply #7 on: July 26, 2022, 04:24:36 AM »
Quote
The overshoot that you're seeing on the gate is probably the inductance of the leads from the CT resonating with the gate capacitance of your IGBTs. Gate capacitance is fixed, you can't do much about that, so anything you can do to reduce the GDT output inductance (shorten the wires, ensure all leads are tightly twisted, etc) will help. It also looks like you're using a 0.1R gate resistor, I'm not an expert on these larger brick IGBTs at all but would have expected this to be closer to 10R. The gate resistor will damp the ringing during turn on at least.
Yes, I agree with above.  However I'd thought you were using 5.1ohm (5R1) gate resistors.  If using 0.1, that explains the rising-edge overshoot.  Looking at the ring, I'd guess that about 5 ohms would be ideal.  (Even faster horizontal scale is good for looking at switching edges, at least down to 1us/div.)  If you already have 5R1 resistors, then higher would help, unless GDT/lead parasitic inductance can be significantly reduced.
Negative overshoot (undershoot) is worse because diodes bypass gate resistors.  Some designs add smaller resistors (say 2 ohms) in series with diodes to reduce undershoot some.  Many designs use TVS diodes instead of zener diodes.  TVS diodes are roughly the same as zener diodes.  (Both are actually avalanche-breakdown, not truly zener.)  TVS diodes are designed to handle much higher peak current.  Clearly your 30V zener diodes aren't clamping undershoot effectively given -40V scope peaks.  Also, TVS diodes come in bidirectional versions, having the back-to-back pair internally in a single package, generally for the same price as unidirectional versions.

BTW, I see what appears to be a circuit breaker on the DC bus.  It does not appear to be a DC-rated breaker.  Normal AC breakers usually don't work well on DC.  Might be OK, however, if between rectifier bridge and bulk caps.  That would provide zero-voltage times for the arc to extinguish, at least if fed by single-phase.  If fed by 3-phase, there will be no zero-voltage times.
« Last Edit: July 26, 2022, 04:34:09 AM by davekni »
David Knierim

Offline Mike

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Re: Gate waveform question
« Reply #8 on: July 26, 2022, 06:08:01 AM »
Quote
However I'd thought you were using 5.1ohm (5R1) gate resistors.
It could be, it's hard to read the resistor codes in the images, it looks like black brown gold, though I wasn't aware that was a valid banding. If it's actually green brown gold it would make a lot more sense.

Offline flyingperson23

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Re: Gate waveform question
« Reply #9 on: July 26, 2022, 03:57:42 PM »
My gate resistors are 5R1. The circuit breaker is just a contactor to discharge the bus capacitors. I'll try lowering the inductance as much as possible. I don't know why the 30v zeners aren't clamping properly, I'll see if I have maybe some 25-30v ones I can test.

Offline Mads Barnkob

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Re: Gate waveform question
« Reply #10 on: July 27, 2022, 02:17:25 PM »
You are building a DRSSTC inverter and not a life saving device. Surgeon precision waveforms are not needed :)

The components are being pushed and their life time in a DRSSTC is already shortened considerable from the rapid and large thermal expansion/contractions.

IGBT gates are rather sturdy and will not break down until 80 VDC+, but limiting gate voltage is also limiting C-E junction current, so its a good idea to keep it under control. More details on all this here: http://kaizerpowerelectronics.dk/tesla-coils/drsstc-design-guide/igbts/

Personally I would not worry or do anything about 10% overshoot at FULL DC BUS voltages! Lower DC BUS voltage testing can give deceiving results in terms of relative spike/overshoot voltages. As its mentioned, the capacitances in the IGBT is fixed and thus will have a greater ratio/influence at lower voltages.
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Re: Gate waveform question
« Reply #10 on: July 27, 2022, 02:17:25 PM »

 


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