Feedback on new freewheeling driver schematic

[Mike]

That's a nice simple option, I think I'll go with that. I was so focused on the rectification that clamping never even crossed my mind. I'll hopefully post updated schematics and board layout layer tonight.

Mike

[Mike]

And here they are, I'll do a last sanity check tomorrow before sending the board files off for manufacture.

Thanks everyone for you assistance, hopefully we've created something that's useful to more than just me, I guess the proof will be in the performance!

[Rafft]

Mike

Interesting circuit!

edit:
have backread topic for more info.

@david
 would your latest schema here be UD2.1b friendly? primarily interested with the phase adj and the OCD section.

cheers
-Ralph

[davekni]

And here they are, I'll do a last sanity check tomorrow before sending the board files off for manufacture.

Just noticed one detail that should be fixed if you plan to use UVL (under-voltage-lockout).  It is wired to OCD, causing two issues.  OCD doesn't disable driver, and OCD is push-pull since using TLV3501.  I'd suggest instead connecting UVL to IC5A-1 (reset-n).  Reset overrides set for Q-n output, so will disable even if interrupt is attempting to enable.  Of course, needs pull-up resistor added too.

Also, I see floating CMOS input pins.  All unused inputs need to be tied to +5V or GND.  Especially critical for unused FF set/reset pins.  Unused inverter inputs should also be tied to +5V or GND or some logic output.

Not important, but OCD is using a fast (and more expensive) comparitor than is needed there.  The list in my LTSpice schematic has many SOT23 options that are fast enough and cheaper.  However, if you prefer your BOM with fewer different parts, TLV3501 should work fine for OCD.

What diode parts are you using for D1 and D2 (feedback clamp diodes)?  I'd designed around fast signal diodes, not schottky.  Schottky diodes may clamp too tightly, especially if self-oscillation frequency is a ways off of operation.  (Self-oscillation frequency might be intentionally set high to force starting at upper pole for QCW coils.)  Also, an SOT23 diode pair would be better matched for better clamping symmetry.

R1 dissipates 36% of the power of R2, so could be smaller if desired.  Of course, no issue leaving it alone.

@david
 would your latest schema here be UD2.1b friendly? primarily interested with the phase adj and the OCD section.

Yes, phase and OCD should work with UD2.1.

[Mike]

Just noticed one detail that should be fixed if you plan to use UVL (under-voltage-lockout).  It is wired to OCD, causing two issues.  OCD doesn't disable driver, and OCD is push-pull since using TLV3501.  I'd suggest instead connecting UVL to IC5A-1 (reset-n).  Reset overrides set for Q-n output, so will disable even if interrupt is attempting to enable.  Of course, needs pull-up resistor added too.

Bother, I'd noted that a while back and decided to use an inverter into IC5A-2 instead of the GND connection (for better or worse, you get zero current switching, but if you're browning out you might just want to be off no matter what and accept the hard switching event). That said, with the overspec'd comparator for the OCD I could drop in an MCP6567 and save the cost of that part and the LM8365 which becomes a pretty significant cost out and avoids routing through the inverter. The two circuits are even laid out adjacently at the moment and would result in less board space... a lot of wins there.

Also, I see floating CMOS input pins.  All unused inputs need to be tied to +5V or GND.  Especially critical for unused FF set/reset pins.  Unused inverter inputs should also be tied to +5V or GND or some logic output.

Good catch, thanks.

I'd designed around fast signal diodes, not schottky.  Schottky diodes may clamp too tightly, especially if self-oscillation frequency is a ways off of operation.  (Self-oscillation frequency might be intentionally set high to force starting at upper pole for QCW coils.)  Also, an SOT23 diode pair would be better matched for better clamping symmetry.

I'd planned on using LS4148s (though I should check the footprint, it's possibly possible to force it onto a SOD-123, but not ideal), I should make that clearer on the schematic, though I've not actually done the BOM roll-up yet. That said a BAV70 BAV99 is quick and easy too and I have plenty of them lying around.

R1 dissipates 36% of the power of R2, so could be smaller if desired.  Of course, no issue leaving it alone.

I noticed this, but had room for the larger footprint. BOM and assembly instructions can make a comment to the fact that it's possible to use a smaller part, the actual cost difference is only a few cents.

Will look at updating when I get home.

Cheers,
Mike.

[Mike]

After lots of time playing around with different UVLO circuits I finally decided on the obvious one which was to use a dual comparator (shared with the over current detection) and the spare FF left over in the second package I needed to introduce for the freewheeling, It's as simple as I can make it (unlike some of the other concepts with diodes and RC constants to try and get fixed times or latching and resetting, etc), efficiently uses "left over" parts which makes it cheap, and it is easy to set the limit. When triggered it will disable the output drive until the next interrupt input. The only downside is it doesn't wait for the next phase edge (i.e. it's asynchronous), but it's debatable which is the more destructive event, a brownout of the driver or a single hard switching event, it depends on so many parameters.

I also fixed up the other basic mistakes I'd missed last time (floating CMOS inputs etc), and changed the input clamping diode to a BAV99 and gotten rid of the phase swap inverter.

Hopefully I've got all the silly mistakes out of the way and won't catch any come build time.

Mike

[davekni]

Hopefully I've got all the silly mistakes out of the way and won't catch any come build time.

Are the two unused 74AHC14 inputs tied to something?  Could even be a two-inverter loop.  Even though outputs aren't used, floating CMOS inputs consume more power and occasionally oscillate at high frequency due to internal/package input-to-output capacitance.  This is common advice on this forum and elsewhere.  I've seen at least one case (likely more) where such oscillation was the likely cause of issues.

Beyond that, I don't see anything important.  A few thoughts still:

Unless routing is very short and clean, I'd add a capacitor from U5B-6 to ground (UVLO comparitor input).  Prevents 5V noise or coupling from making erroneous spikes on UVLO.  (Cap on OCD comparitor + input is there for same reason.)

R20 can be 10k to reduce BOM part types.  Given the cap to filter noise, value doesn't matter much.  I'd randomly picked 2k initially.

I'd make R30 2k, so 24V divides down to 4V.  No point in having so much unused range on UVLO adjustment.  Unless you are concerned about 24V going above 30V and over-ranging comparitor input.

The only downside is it does wait for the next phase input which could be argued is too late in a brownout situation, but it avoids hard switching which is also potentially energetic.

I'm not seeing this.  Have you simulated brown-out?  Don't think it's critical.  I'm not seeing any value in putting the FF in UVLO path.  On rising edge of 24V, it doesn't matter if an interrupt pulse is occurring.  UVLO will just make it a shorter pulse (later start, same end).  On falling 24V, UVLO immediately resets IC5B, which immediately resets IC5A, setting DISABLE high.

Hysteresis would be helpful on UVLO.  I believe most dedicated UVLO chips include that.  A resistor from U5B-7 to U5B-5.  Otherwise an insufficient P24V supply or slow brownout condition could lead to oscillation.  Disable reduces current draw, +24V increases, operation starts, +24V decreases, etc.  (Or, make UVLO synchronization functional so it doesn't cause repeated hard switching events.)

[Mike]

Are the two unused 74AHC14 inputs tied to something?

Drat, oh well, nothing a bit of wire can't fix. An unfortunate case of out of sigh out of mind occurring there.

Unless routing is very short and clean, I'd add a capacitor from U5B-6 to ground (UVLO comparitor input).  Prevents 5V noise or coupling from making erroneous spikes on UVLO.  (Cap on OCD comparitor + input is there for same reason.)

It's what I would describe as "so-so", probably could use the cap yes.

I'm not seeing this.  Have you simulated brown-out?  Don't think it's critical.  I'm not seeing any value in putting the FF in UVLO path.  On rising edge of 24V, it doesn't matter if an interrupt pulse is occurring.  UVLO will just make it a shorter pulse (later start, same end).  On falling 24V, UVLO immediately resets IC5B, which immediately resets IC5A, setting DISABLE high.

You're too fast off the mark, that was only up for a minute before I corrected myself in an edit (sorry). It is asynchronous you're correct.
The flipflop is there for short duration brown outs. It's use may be a little unnecessary but the basic though was a marginal power supply might dip in and out of brownout under heavy load and should be disabled. I don't want the brownout disabling the output on every half cycle and causing excessive hard switching. FF means it's disabled until the next interrupt edge. This is what terminates the first burst in the simulation files.

Hysteresis is probably a good idea still, but didn't seem necessary in conjunction with the FF.

I've update the schematic already with the ground & value changes you discussed. Boards were ordered this morning on Rev 02. Your recommendations are all reasonably easily implemented on the board with a few bodges.

[davekni]

The flipflop is there for short duration brown outs. It's use may be a little unnecessary but the basic though was a marginal power supply might dip in and out of brownout under heavy load and should be disabled. I don't want the brownout disabling the output on every half cycle and causing excessive hard switching. FF means it's disabled until the next interrupt edge. This is what terminates the first burst in the simulation files.

Hysteresis is probably a good idea still, but didn't seem necessary in conjunction with the FF.

Agree, FF limits hard switching to maximum of interrupt frequency, making hysteresis of low importance.  Or, you could add hysteresis and skip FF.  Hysteresis combined with +24V filter caps will limit frequency of UVLO cycling, to a similar range depending on interrupt frequency and hysteresis voltage delta.

I've update the schematic already with the ground & value changes you discussed. Boards were ordered this morning on Rev 02. Your recommendations are all reasonably easily implemented on the board with a few bodges.

Looks good!  I'm not spotting anything else to suggest.

[Hydron]

Good to see you're using a comparator for UVLO - there are some gotchas with using a LM8365! As the sensing voltage also powers the UVLO chip it will assert a UVLO as the voltage drops below it's setpoint, but then stop asserting it again below about 8V input, as this is the point where the divided-down 24V will fall below the 1V minimum input rating of the UVLO circuit (assuming that 24V nominal = 3V input to the LM8365, which was the original setting when this circuit was first whipped up). At this point the logic and gate drivers will still be working, so a new interrupter input will cause it to try and drive the IGBTs again, but with only 8V bad things are likely to happen.

This can be avoided by making a single UVLO event latch off the driver properly until power is cycled (rather than re-using the OCD input), or by using a circuit that doesn't do sensing and power from the same input (like your comparator). The former is probably best, as any UVLO event is cause for checking things out before continuing. If someone wants to keep using a LM8365 then I think the problem can be solved by using a couple of extra resistors and a diode, to clamp the minimum UVLO input voltage to something between the LM8365 trip point and it's 1V minimum input (e.g. divide the 5V rail down to 2.5V with a couple of 1k resistors, then connect that via a diode to the LM8365 input node).

I will admit I am partly responsible for the above problem - when I made my own modifications to a UD2.x design years ago I threw in the LM8365 as a quick hack way to get a UVLO, basically as I had one on hand at the time (and didn't think too much about the behaviour at very low input voltages). It was then copied and added as a standard feature before people realised the issue with using this type of chip!

[Mike]

Looks good!  I'm not spotting anything else to suggest.

Time will tell!

This can be avoided by making a single UVLO event latch off the driver properly until power is cycled (rather than re-using the OCD input)

This was one of the solutions I looked at (using a diode between the comparator output and the non-inverting input so it would latch off till a power reset). It's definitely the safe option, my main reason for not going that was was not trusting that there could be no other event that could accidentally trigger the latch. There's some poor logic in that reasoning I'll admit, but a "self resetting" safety is less likely to be the end of a show if layout issues (board or coil) or other unforeseen events cause that part of the circuit to misbehave temporarily. It also started getting a little complicated trying to ensure the correct state at start up - doable, but messy.

Thanks again for everyone's feedback, I'll update when I receive and build / test the boards. If there are any other suggestions for improvements, there's always the next revision!

Mike