Please keep questions on-topic, this question has nothing to do with Bleeder resistors.

You've also already asked this in other threads - be patient and someone will likely answer a reasonable question (as I did in the other thread where you asked). I suggest going and reading the forum rules, specifically #3.

Just run the driver at a voltage lower than 24V, I'd suggest something in the 15-18V range. Then you can use a 1:1 CT for easiest and best results.

You are correct that the UVLO has a major flaw at <8V - unfortunately it'd been copied by others before I found the issue. See also another post by me about it: https://highvoltageforum.net/index.php?topic=2054.msg15613#msg15613

You could wind the GDTs with something like RG-174 or similar small diameter coax - voltage rating should be >1kV (look it up for whatever cable you find) and you can run the primary winding on the shield and the secondary on the core for very high coupling (low leakage).

Looks very nice for a first build!

Looks good - I'd certainly noticed some nasty switching early in a burst, though I'm not sure whether it was due to this bug (I assumed it was from mismatch between start_freq and actual resonant freq). Will certainly need to give the fix a go myself.

Are your changes in the digipot branch of Netzpfuscher's repo?

Might be useful to see the PCB layout of the bridge and gate drive components. I've been battling some turn-off overshoot issues myself and PCB layout made a huge difference to their magnitude (and yes I did see some overshoot with 80% magnitude in some of my earlier layouts).

Couple of other options maybe worth trying if you think it's definitely the turn-off spikes killing the IGBTs:
- Using a snubber like the one in the attachment - would need a tight layout for the D and C to minimise stray L (resistor doesn't sit in the fast current path so isn't critical), and a diode that starts forward conduction very quickly. This type of snubber only clamps voltages above the steady state bus voltage so power dissipation is not a big concern as it can be with other styles. This is on my list to try if I do another PCB spin (especially if I can find some appropriate parts in JLC's assembly list).
- If you're turning the IGBTs off via a gate resistor (as opposed to just totally bypassing with a diode for turn-off) then you might be able to tame the spikes a little by using TVS diodes to clamp the voltage between gate and collector (NOT emitter) to ~400V or so (will end up clamping a fair bit higher because of TVS behaviour). This will help reduce spikes by slowing turn-off when it causes high Vce voltages, though in extreme cases it may risk some cross-conduction though if it delays turn-off too long.
- Have a go with Dave's GDT buffer - it did improve the behaviour on my coil: https://highvoltageforum.net/index.php?topic=2389.0

Improved PCB layout made a much larger difference than trying the TVS clamping trick in my case though so I'd start there. 4 layer boards are crazy cheap these days and give you a lot of flexibility in reducing loop area etc (though take care not to end up with too much stray C between gate and collector). I'll try and tidy up my own latest half-bridge board design and release the PCBs this weekend, though I haven't gotten them going at full bus voltage yet either (or with the full planned 8 half-bridges - just testing with 2 for now and a 4*higher-Z tank).
I'm also trying to hard switch >100A too (without avalanche rated parts) so I'm playing on hard mode, as the 4 IGBTs I've killed so far attest to.

Looks good! BTW when you get pissed off with denting the aluminium ducting toroid every time you look at it wrong, invest in some stainless single walled flu-liner - it's not indestructible but will shrug off something that would totally crumple the aluminium stuff.

Great timing on the update - I'm in the middle of laying out a GDT board to be driven from a UD3.x controller, so while I won't be using your new PCB layout some of the schematic changes are certainly of interest. Once done and tested I'll be uploading my designs btw, though they are going to be pretty customised for my specific project.

The thing I'm most interested in is the GDT mosfets and their drive circuit:
- is there a preferred output P+N-ch mosfet you're aiming at and have tested? I've got some AOD609s and the good old FDD8424Hs, but those aren't always easy to find, and the power-SO-8 package style you're using here seems more standardised. I might see if I can hack a footprint up enough to allow compatibility with the SO-8 as well as the TO-252 styles in my design.
- What sort of gate threshold variation do you think requires the passive deadtime network? I'm assuming that gate charge variation between P and N could also have an effect too if the difference is large enough? I must admit that I haven't looked much at this part of the gate drive circuit, as with the FDD8424Hs it's basically just always seemed to work OK - my measurements and simulation have mostly been of the GDT itself and the IGBT drive network.
- Have you noticed any performance differences with 5V vs higher (e.g. 12V) UCC drive IC voltage? It's certainly a bit lower power (and easier, given 5V is already needed) to just run it on 5V and skip the intermediate supply between that and the IGBT drive voltage.

Finally a comment about the bipolar LEM current sensors - if all they are doing is looking at the current from rectified mains charging the bulk bus capacitors, then there may be an easier and cheaper way of doing this. If you use a 50/60Hz capable current transformer on the incoming AC line (i.e. before the rectifier) then you can rectify it's output using a small bridge and feed this into the input (with burden resistor), with no power supply required at all - as it's on the AC side then a simple CT is enough. If a voltage doubling rectifier is used for the bus then the burden resistor value set in the UD3 cli/gui should be entered as twice the real value though (OR the CT ratio as half the real ratio), as the CT measures twice the actual DC bus current with the doubling rectifier, so it needs to be scaled to the real value and this is an easy way to do it.

I've only made up one board and am about to go on holiday for a couple of weeks, but either the board or the buffer (which I placed on this one board) or both has made a spectacular difference to overshoot on turn-off. I'll try and build another if I have time with the "conventional" (un-buffered) option as a comparison to take the PCB change out of the equation. Will post pics etc (or at least PCB renders and design files) when I get a chance.

Had a very quick investigation, looks like the improvement was a bit of column A, bit of column B. New PCB seems to have made the biggest change, but the buffer improves it even more. See attached pics, first is with the buffer (ignore the yellow trace, that's from the other igbt and the diff probe is picking up a bunch of nasty stuff from the other half bridge), second is without. Orange is Vce, green is Vge, blue is current. Will upload pics of the half bridge board when I'm not posting from my phone.