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Topics - davekni

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1
Beginners / GDT (Gate Drive Transformer) tutorial
« on: November 28, 2021, 11:40:56 PM »
Hopefully this isn't wasted redundant work.  I've seen many builds with good GDT construction, using both halves of each twisted pair.  However, all the GDT construction guides I've found use a single primary wire.  Below is construction of a half-bridge GDT using two twisted pairs from CAT5 cable.  This is easier to see in pictures.  Extension to full-bridge isn't difficult.  Use four pairs, with four paralleled windings for primary, one wire from each pair.  (BTW, CAT5 isn't necessary.  If starting with single wires, twist pairs together, and use those pairs exactly as you would with pairs extracted from CAT5 cable.)

Start with a suitable high-permeability ferrite core.  (Some options listed at the end.)  The core I'm using here works, although the shape is not typical.  Pay attention to winding technique, not so much to core shape.

Wind two (for half-bridge) twisted pairs around the core.  More discussion about the number of turns to follow.  I'm using 4 turns here.  Mark the starting end of all four wires for later identification.  Here I've "marked" starting ends by length (short), with the tail ends left longer.  Other (preferred) options are to add bits of tape to the starting ends or strip insulation from the starting ends only.





Untwist the pairs almost to the core:



Twist each wire (each winding) with itself all the way back to where the pair twisting starts.  Don't leave any significant loop area of untwisted wire:



Pair one winding of each pair together for the primary.  I've chosen the lighter-color wire of each pair for simplicity, white and light-blue.  Most important: connect the two starting ends (short ends or stripped ends or however you marked them) together, then the two tail ends together.  If pairing is swapped, driver can be damaged by the shorted load.  (Test at very-low duty cycle initially just in case of error.)  The remaining winding of each pair is for an IGBT.  Starting end of one IGBT winding is gate.  Starting end of other IGBT winding is emitter of other IGBT.



Since I hadn't used tape to identify starting ends at the beginning, I added tape now.  Then cut the tail ends to length and strip.  Connect the two primary tail ends together:



The reason for the twisting is to minimize leakage inductance.  Leakage inductance slows down gate waveforms and causes overshoot and undershoot and generally-sloppy gate drive.  Twisting forces the wires to remain close together with little loop area between wires for magnetic field to slip through.  Best to maintain this pairing all the way to the driver for primary and all the way to gate and emitter terminals of IGBTs (or FETs) for the secondaries.  Avoid excess loop area when adding gate series resistors.  Keep the emitter wire adjacent the resistor to minimize loop area.

Now for a bit about cores and turns.  I'll add a second post on measuring cores and finished GDTs, a bit more advanced topic.
Toroid shape is generally preferred, but E-cores work if ungapped (no air gap or spacer between the two halves).
Most important two parameters are:
     Core material (reasonably-high permeability and saturation flux density).
     Core cross-sectional area.  Picture the area of a core slice inside one turn of the GDT winding.
Iron and other compressed-powder cores never work well.  Most (but not all) ferrite materials are OK.
Low-frequency EMI suppression cores are reasonable.  That is what I used above.  Most larger EMI cores are low-frequency, so workable.  This includes common-mode chokes found in power supplies.  (Remove existing windings.)  Such EMI materials include:
3C11, 3E6, 3E12, 3E10, 3E15, 3E25, 3E26, 3E27, 3E65
More ideal ferrite materials are generally designed for switching power supply transformers etc.  These include:
PC40, PC200
N27, N30, N35, N41, N49, N51, N72, N87, N88, N92, N95, N96, N97
T35, T37, T37, T38, T46, T57, T65, T66
3C90 through 3C97

Concerning cross-sectional area, more is better, within constraints of fitting the GDT mechanically into the build.  The core I used above is 28mm long, 14mm ID, 28mm OD.  The ring is 7mm thick (0.5 * (OD - ID)).  So cross-sectional area is 7mm thick * 28mm long = 196mm^2.  If using a more-typical ring toroid, the formula includes a factor of PI/4:  Area = length * 0.5 * (OD - ID) * PI / 4.

In general, look for cross-sectional area to be at 50mm^2 or more.  A bit smaller is fine for high-frequency Tesla coils.  Larger for low-frequency coils.  10 turns is usually plenty.  Excess turns increases wire length and therefore leakage inductance.  The above example is 4 turns.

(All my GDTs have either 2 turns or 3 turns.  That works with large area cores and careful measurement to make sure its enough.  A few more turns is generally safer.  Too many turns causes subtle issues due to leakage inductance.  Too few turns is more catastrophic, possibly damaging the driver and/or IGBTs when the core saturates.)

Here's a great picture from Mads of a full H-Bridge GDT constructed this way:
https://highvoltageforum.net/index.php?topic=1856.msg13969#msg13969

A couple other posts with images that aren't quite as obvious.  For this first, look at the upper GDT wound with CAT5 cable including jacket:
https://highvoltageforum.net/index.php?topic=588.msg3779#msg3779
And this 3-turn GDT from my bridge tutorial:
https://highvoltageforum.net/index.php?topic=1324.msg9886#msg9886

2
Capacitor Banks / 3kJ coin shrinking
« on: October 21, 2021, 05:48:49 AM »
My 2002 coin-shrinker is built into a corner of my garage semi-permanently.  Wired into my house through 1meg array of power resistors, avoiding exposure to lethal current when charging and triggering.  Cap is an ancient oil/paper pulse unit, 14uF at 20kV, which I run at ~20.5kV for ~3kJ energy.  Over 1500 coins shrank in its 19 year life, with a few repairs along the way.

Optimization is different depending on capacitance.  At 14uF, two layer coils are better than the more common 1-layer coils.  Magnet wire is terrible, immediately arcing between layers.  Even with wraps of tape between layers isn't enough.  Enamel cracks as wire stretches, and arc paths develop.  Thin stretchy insulation over stranded wire works best for me (radiation-crosslinked PVC).  Broken strands overlap, so conduct better as wire stretches.  Coil shrinks axially and expands radially as it explodes.  My optimum ended up as 2x9 (2 layers of 9 turns each) of 18AWG.  Started with 4x6. but 2x9 passes through optimum shape (wire close to quarter rim) as it explodes.

A few pictures for comparison.  I haven't made a video.

Original wood containment box, lasted about 15 shots before 2x6 boards split.



After 3 rebuilds, changed to 1/4" alominum cylinder.









Coil voltage at 5kV/div.  Pulse lasts about 17us.  This short pulse time maximizes shrinking, but does leave the outer rim thicker than the center.  Skin effect prevents coin current from penetrating to the coin center.  See above image.






3
Electronic Circuits / Micro-power continuity checker.
« on: July 20, 2021, 05:37:36 AM »
About 15 years ago I built a couple simple continuity checkers, one for home and one for work.  They apply low voltage to avoid forward diode junction conduction and light an LED when resistance is below about 10 ohms.  Power is from a single 18650 LiIon cell.  I find them very convenient - probing an ECB to see which side of a bypass capacitor is ground, checking for hidden solder bridges under parts, etc.  However, these draw enough quiescent current that an on/off switch is necessary.

Last weekend I made two new continuity checkers drawing only 10uA quiescent.  Also reduced threshold resistance to between 1 and 2 ohms.  No on/off switch to forget to switch and battery life of 5-10 years between charges. :)

Normal people would use a micro-power opamp for such a circuit.  Being abnormal and fond of discrete circuity, mine uses three transistors instead:



Dremel-tool cut circuit board:



Finished continuity checker.  Most of the volume is the 18650 LiIon cell.  Board and probe tip are taped to the cell.





The circuit can easily be made in reverse, using PNP transistors and an NFET.  (Actually, one of the two I made is reversed.)  Power supply is reversed too.  I prefer the version shown here, as one probe is the negative supply which is battery case.  Makes accidental shorts of the battery less likely.

4
DSLR / Global shutter synchronized to arcs?
« on: July 19, 2021, 06:32:35 AM »
Just a thought at this point.  Does anyone have a global-shutter camera?  It would be interesting to sync the camera exposure with DRSSTC sparks.  With a properly timed and short exposure it should be possible to get good arc images in brighter background situations.  Synchronized global-shutter video could allow daytime DRSSTC testing while still monitoring for errant sparks.

Two possibilities for synchronizing.  The likely-easier option would be to use a camera output intended for strobe-light triggering to trigger single DRSSTC enable pulses.  The down-side of this option is longer exposure times (unless the camera has an option to generate a trigger slightly prior to shutter opening.)

The other possibility is to trigger camera exposure from the DRSSTC enable pulse, perhaps with some controlled added delay.  Then the exposure could be short, covering just the active arc portion of the DRSSTC pulse.

I've built similar systems at work for strobed microscope viewing of ink drops.  Unfortunately, I don't think there's any equipment available to borrow.  I see cheap (~$70) global-shutter webcams from China.  Can't find any information about options for trigger input or strobe output.  The cheapest global-shutter camera I've found that lists trigger capability is $200+shipping.  Perhaps someday when my project list gets short ;) I'll buy a camera and experiment.  That is if no one else has tried it first.

5
Still in the planning/simulation stage, but time to seek input/suggestions.  This is an induction heating driver powered directly from rectified 240Vac line.  No bulk capacitance, so induction power will track line voltage.  Output will be ferrite-transformer coupled to work coil, for both isolation and to reduce voltage.

    Up to 10kW (for use on a 40A 240V circuit).
    ~100kHz frequency (perhaps 80kHz minimum, ~200kHz maximum)
    Resonant capacitors on primary side.  (Transformer handles resonant current.)
    IXYH24N170CV1 24A 1700V TO247 IGBTs, 4 total, 2 parallel pairs.
    SCT2H12NY 4A 1700V SiC FET for gate drive to IGBTs
    GD10MPS17H 10A 1700V SiC diodes across IGBTs (which have no internal diodes)
        (ZVS circuit ideally has no reverse IGBT voltage, but slow turn-off requires diodes for momentary conduction.)

My thought for the LARGE output transformer:
    4:1 ratio (with the idea to match voltage from 60V direct-drive ZVS systems).  Would love to learn more about inductance and frequency of typical work coils for <= 10kW power.
    Two sets of large U93/76/30 U-cores arranged to look like an even larger E-core set.
    4-turn primary made of 90mm x 0.2mm copper foil wound as four layers around E-core center.  Leads (copper pipe or bus-bar) exit one end of the E-core set.
    1-turn secondary, 90mm x 0.5mm copper, over (around) primary.
    Windings spaced radially to allow for axial forced-air cooling.
    Each work coil can be soldered to its own 1-turn primary if desired.  Core is separable, so new secondaries can be slid into place.
    90mm x 0.5mm secondary winding can be extended as parallel-plate leads in order to locate work coil farther from transformer without adding significant additional parasitic inductance.

For circuitry, here's my modifications to the simple ZVS oscillator in order to accommodate larger forward drop of HV devices while keeping Vge low voltage close to 0V:


Any feedback and suggestions would be appreciated.  Likely to be some time before this project gets to the top of my list.

Also thinking of a variation w/o ferrite transformer for driving my SSTC.

6
For comparison, I made a 13.56MHz (more common ISM freuency) HFSSTC.  As with my initial 6.78MHz version, gate drive is from a crystal oscillator, not from drain feedback.  The arc plasma behaves much more like a flame at 13.56MHz than at 6.78MHz.

Circuit is similar.  Ended up with 26pF of external drain-source capacitance.  Not planned initially, but routing FET source (ground) as a plane adjacent the heat-sink (FET drain) added this capacitance.  As Steve pointed out, added capacitance widens drain pulses, lowering peak voltage.



Running inside at 450W (90V 5A) from bench supplies:



Simulation schematic:  (Full SiC FET part number is NVH4L160N120SC1)



Ran into one new issue initially.  Since these are actually dual-resonant (DRSSTC), the upper pole ended up at the second harmonic (27.12MHz).  Here's a scope capture at low power (no arc) showing the harmonic.  Black is SiC FET gate (at 5V/div.  Probe readout pin is missing), green is FET drain, cyan (light blue) is one side of GDT input (for trigger), and red is antenna (scope probe) near secondary:



Reducing the breakout size fixed the harmonic issue by raising the upper pole frequency above 2x lower pole.  Perhaps second-harmonic isn't really an issue.  I never ran it that way at high power.  Arcs are larger than the initial secondary structure, but are damped (resistive) enough to not show significant second-harmonic.

After fixing, here's scope traces running at 450W:



Same scope traces except without gate, running ~900W in my garage:



Running normally with carbon rod breakout, up to 1.1kW DC input power:
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There is room to push power higher, as drain peaks are aroun 800V.  For now it is limited by the voltage of rectified 120VAC line.

With glass tube over stainless for sodium yellow:
/>
Strontium chloride on breakout for red:
/>
Boron (ammonium borate) for green:
/>
Finally, just for fun, steel spring breakout (sparkler):
/>

7
Finally having some success with a fixed-frequency HFSSTC.  Unlike most coils, gate drive is from a crystal oscillator (with amplification), not feedback from the drain circuit.  Frequency is the lowest ISM allocation at 6.78MHz.  Otherwise this is the same as other class-E circuits.

Power is somewhat limited so far, about 800 watts.  Hope to get a little higher.  With a fixed frequency, the coil must be tuned to achieve class-E operation before starting an arc.  Gate-drive frequency does not track increasing arc capacitance.  Larger arcs pull the coil farther out-of-tune.  The FET sees much more reactive power than real power.  To keep the FET within voltage and current ratings, FET reactive power can't get too high.  That makes real power even more limited.

I'm experimenting with a 4S2 (NiZn) ferrite for adjusting primary coil inductance.  Can't get more than about 1% frequency range (2% inductance range) before the ferrite gets too hot.  The clean (and more complex) solution to a fixed-frequency HFSSTC would be to use a PLL to start at a higher frequency, then lock to the desired fixed frequency once the arc is large enough.

Here's my simulation schematic.  The 3.3V pulse generator V3 simulates the crystal oscillator.  Amplifier stage is ZVS feeding a GDT.  GDT leakage inductance is the ZVS resonant inductance, with gate voltage opposite phase to GDT input due to this tuned leakage inductance.  FET is a 17A 1200V SiC NVH4L160N120SC1.


Breakout is a carbon rod following Steve Ward's example.  The arc wanders around the rod top and upper sides.  Not sure if this is due to the lower-than-typical frequency, or just that the breakout doesn't get hot enough for thermionic emission.  Any thoughts here?

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BTW, the backdrop in the video is a white wall with bright room illumination.  I've manually set camera exposure low to avoid arc wash-out.

Edit:  Fixed one schematic error.  I'd lowered breakout capacitance and forgot to add in the corresponding secondary coil capacitance, now as C5.

8
I made an optics setup that is a mix of conventional and projected Schlieren.  I think this was called "multiple Schlieren" somewhere, but can't find that reference.

This setup is close to conventional Schlieren, but with two key differences.  First, instead of a camera, a lens focuses the image onto a wall or screen.  The second difference is what makes it bright enough to allow projection.  Instead of a single point light source and single knife-edge, this uses a line-array light source and matching line-array shadow mask instead of a single knife edge.

The light source is a 6-watt white LED inside a 38mm diameter parabolic reflector.  A bright narrow-beam commercial flashlight will work just as well.  The camera-replacement is a 55mm diameter +1 closeup lens.  (It actually measures 1.2 diopter, but was sold as +1.  A true 1-diopter lens projects a somewhat larger image a bit farther away.)  Covering both the light source and lens is a vertical grid of lines at 1mm pitch, 0.5mm black and 0.5mm clear.  This shadow-mask was printed with a standard laser printer onto transparency film.

The most expensive piece is a telescope mirror, 8" (203mm) diameter in this case.  Cost was $110.  A spherical mirror is ideal for Schlieren.  This one is parabolic, which is close enough.  (Found a similarly-priced spherical mirror shortly after purchasing this one.)  The next most expensive item would be a bright LED flashlight, perhaps $30-$40 for a good one.  For this project I built my own with an LED, reflector, and heat-sink.  A +1 close-up lens can be found for under $10.  The rest is building materials, wood/plastic/screws/etc., and a few magnets.  The shadow-mask is a piece of transparency film printed with a laser printer.

The shadow-mask is mounted 1500mm from the mirror at the center of its curvature.  The magnets allow sliding the light and lens assembly to the center, as my wood frame is not exact.  The mirror has a 750mm focal length, with radius of curvature being twice focal length.  (It was listed as D203F800, but was really D203F750.)  The light source and lens mount behind the shadow mask.  Distance is not critical - gaps between the lens and/or light and shadow mask are fine.

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This printed shadow mask works fairly well, but isn't ideal.  Light passes twice through the transparency film, which isn't AR coated.  Also the lines are not as high optical density as I'd like.  Not sure how easy and/or expensive it would be to procure a better mask, either etched metal or chrome on AR-coated glass.  I tried an array of 0.5 x 3mm carbon-fiber strips.  That made artifacts due to it's 3mm depth and reflections of glancing-angle rays hitting the internal edges of the strips.  Extinction ratio was well better though.  I may try double-printing the transparency film, either repeat-printing the same side or duplex (printing the opposite side).  Issue will be alignment between the two printing passes.  Any suggestions for a line shadow mask?

9
A basic half-bridge SSTC makes a great first electronic Tesla coil project.  For example, this SSTC-1 design from KaizerPowerElectronics:
http://kaizerpowerelectronics.dk/tesla-coils/kaizer-sstc-i/

There are two sections to the electronics.  The driver:
http://kaizerpowerelectronics.dk/wp-content/gallery/2009_01_22_-_kaizer_SSTC_I/KaizerSSTCIdriverschematic.gif

And the half-bridge:
http://kaizerpowerelectronics.dk/wp-content/gallery/2009_01_22_-_kaizer_SSTC_I/KaizerSSTCIbridgeschematic.gif

Many first-time builds have problems due to half-bridge construction.  Wires and even device leads have inductance, often enough to disrupt operation.  A wired bridge certlainly can work, as shown in the above links.  However, lower parasitic inductance reduces voltage spikes, making for a more robust build.  Below is a simple technique (no ECBs) for building a half-bridge with low parasitic inductance.  Part labels are from the above KaizerPowerElectronics SSTC-1 bridge schematic.

The key to low inductance is copper planes.  Ideally the planes are on opposite sides of an insulating layer.  Four rectangles of copper foil tape is all it takes for a bridge, two on each side of a flat insulating layer.  Fiberglass or other phenolyc would be ideal for soldering temperatures, but may not be readily available.  Here I use 2mm-thick polycarbonate.  Even though the melting temperature is below soldering temperature, it works well.  Perhaps counter-intuitive, but it works best to use a hot soldering iron.  A hot iron can make joints quickly before the polycarbonate has time to melt.

Apply two rectangles of copper tape to one side of the insulating sheet horizontally, with a small gap between rectangles.  Apply the other two copper rectangles to the other side vertically, again with a small gap.  The gaps form a cross shape.

Simplest construction is to solder parts along the edges.  It's not space-efficient, but works well:





For better space efficiency, parts can be mounted on top of the foil/insulator sandwich.  This requires drilling a couple holes for one lead each of C8 and C9, and cutting a larger clearance hole in the top copper foil.  One lead each of C8 and C9 is bent out horizontally to solder to top copper.  The other lead goes through the hole, then bent horizontally and soldered.







Size of these copper planes and insulator is not at all critical.  Make them fit the pars being used.  The key is just overlapping planes instead of wires, and minimal lead length from part bodies to copper planes.

This can alternatively be constructed from double-sided copper-clad board.  Just cut a horizontal gap in top-side copper and a vertical gap in bottom-side copper.  I find that a dremel-tool cut-off wheel works well.  A hobby knife or round file can work too.  For clearance around through-holes, a few turns by hand of a large drill bit works nicely.  (Not for foil, which tends to tear.)

Notice that the gate-drive wires solder to the FETs (IGBTs in my sample) close to the device bodies, not to the foil planes.  This minimizes source (emitter) inductance that is shared between gate-drive and output current paths.

It is best to use copper foil tape that is wide enough, then cut it down as needed.  Soldering multiple strips of copper tape together is difficult.  Solder resists bridging between sections, as it doesn't wet the sticky layer.  Here's two example EBay listings for 50mm tape (no indorsement - just search result):
https://www.ebay.com/itm/Copper-Foil-Tape-EMI-shielding-for-Guitar-Slug-and-snail-barrier-6x50mm-Folded/273719723048
https://www.ebay.com/itm/3m-50mm-Guitar-Copper-Foil-EMI-Shielding-Tape-for-Electric-Guitar/133531273698

BTW, the top and bottom copper layers can be swapped.  There's nothing magic about which signals are on top.  Also, this works for a full-bridge, by removing C8 and C9 and adding two more IGBTs/FETs along the edge opposite the existing two.

10
This may seem like a strange concern, but I'm wondering about the possibility of internal IGBT brick gate resistor failure.  I'm designing a QCW for long 100ms pulses starting around 170kHz.  Planning to use CM600DY-13T half-bridge bricks.  Internal gate resistance is 1-ohm, with recommended 1-ohm external.  Running +-20V gate drive into 6uC/gate at 170kHz is 41watts/gate or 82watts/brick.  With external 1-ohm, half that 82watts is external and half internal.  Thus the internal gate resistors are running at 41watts/brick.  If the internal gate resistors are thick-film and relatively small, I wonder about long-term failure.  Thick-film resistors don't survive power pulses very well.

For those of you who have deconstructed IGBT bricks:  How robust to the gate resistors appear?  Is it possible to determine resistor element technology (thin-film, thick-film, or wire-wound)?  Are the resistors thermally connected to the base, or suspended above?  Should I be concerned about 41 watts for a CM600DY-13T brick gate drive internal power?

Thank you all in advance for advice.

11
Inspired by Jan's impressive ferrite-core QCW coil here:
https://highvoltageforum.net/index.php?topic=1073.0

and his wishing that the primary could be adjusted, I'm starting a project to make a QCW with replaceable ferrite-core primary.  The idea is to pot the inside of the secondary with a cavity for the primary.  However, a plain cavity would form corona discharge between the inside surface of the cavity and the primary.  So, here's the secondary form and cavity I plan to pot inside in a couple days:





The cavity is a Faraday cage with no closed loops.  All the wires connect at only the top.  Wires will all be inside the potting material.  At the bottom, I'll connect ONE of the wires to ground.  That way the internal electric field of the secondary will return to the Faraday cage within potting material.  Internal electric field around the primary will be due to only the primary voltage, low enough to avoid corona.  Magnetic field will be free to pass between Faraday cage wires.

Anyone see any issues before I mix and pour epoxy?  I will be using vacuum to remove as much air as possible, per what I've learned on this forum.

This is the first step of a long project.  Haven't built any of the electronics yet.  My aim is to explore lower frequency and longer ramp times than typical for QCW, to see if slow ramps can compensate for lower frequency.  Somewhere around 170kHz and 100ms ramp.

12
This is an optically-isolated scope probe for use in probing high-side gate drive and other such non-ground-referenced signals.  Also eventually plan to use a pair of these to measure charge transfer on top of my DRSSTC, from secondary to top-load and from secondary to breakout point.

This probe uses standard 1mm-core plastic optical fiber.  A "T-1 3/4" (5mm-diameter) LED feeds the fiber with light proportional to input signal plus a fixed DC offset.  Photodiode receiver amplifies the light signal and subtracts the fixed offset.  Most newer efficient LEDs have surprisingly linear drive-current to light-output.  Here's a picture of the probe, driver and receiver and fiber.  Each end is powered by a flat 4V lithium-ion cell under the ECB.



Bandwidth without any compensation for LED capacitance is just over 4MHz.  With an added R+C to peak LED current, bandwidth is roughly 10MHz.  (I tried a couple LEDs packaged specifically for 1mm-core 2.2mm OD optical fiber.  They were higher-bandwidth, but much less efficient.  Light coupled into the fiber was much lower, so would have required higher receiver gain and associated higher noise.)  Below are scope traces of a 12V square wave out of a UCC27525 gate-driver chip.  Channel 4 is with a normal 10x scope probe.  Channel 1 is this isolated probe output.  Both scope channels are set to 20MHz bandwidth limit.  Notice that this optical probe output has roughly twice the rise/fall times, so about half the bandwidth.  It also has more delay due to the coil of fiber.







Input divider resistors for this first unit are designed for gate-drive scoping, +-20V.  Output to scope is +-200mV (100x attenuation).  Input impedance is 30k-ohms.  Low enough to avoid needing to tweak input attenuator compensation capacitors, but high enough to not significantly load gate-drive signals.  Here's the driver schematic including R10+C3 peaking to compensate for LED capacitance:



And the receiver using the IF-D91 photociode designed for plastic fiber:



I found two successful ways to couple the 5mm OD LED to 2.2mm OD (1.0mm core) fiber.  One is to drill a 2.2mm hole in the LED deep enough to almost hit the bond wire, then glue one end of the fiber into the hole.  Glue makes reasonable optical matching (similar index of refraction to the LED housing and fiber core).  Here's a close-up of the LED with fiber glued into it:



The other option is to grind/sand down the end of the LED to make a flat surface, again almost to the bond wire.  Didn't have any good way to polish the surface, so instead glued a small piece of mylar to the end to make a shiny surface.  Then used a short piece of 3/16" ID (just under 5mm) rubber tubing to couple the LED to fiber.  I'd found some fiber with an outer jacket that was conveniently 5mm OD.  The 3/16" ID tubing could either join the LED directly to this fiber, or I could remove a short section of the large fiber's outer jacket, join that section to the LED with rubber tubing, then insert normal 2.2mm OD fiber into that piece of jacket.

Finally, on the outside chance that anyone wants to experiment with this design unmodified, here are the zipped gerber files:

* fiber_scope.zip


13
Sell / Buy / Trade / Found some 20mF 450V caps on EBay in USA
« on: July 17, 2020, 07:02:36 AM »
Not my listing, but I just bought some of these large 20mF (20,000uF) 450V electrolytic capacitors:
https://www.ebay.com/itm/United-Chemi-Con-Electrolytic-Capacitor-20000uF-450V-New-Open-Box-Reformed/401984486380?ssPageName=STRK%3AMEBIDX%3AIT&_trksid=p2057872.m2749.l2649

They look good in bench-testing, 18mF measured with 4-5 milliohms ESR in the 10kHz-100kHz range.  (Tested with a square current pulse, not sine-wave AC.)  Do be careful with these or any such large caps.  It appears I've caused myself some permanent hearing loss by a single incident of accidentally shorting one of these when charged to ~400V . :(

14
I purchased some bulk caps on EBay for DRSSTC use, so was testing them.  While connecting a resistor to discharge a cap after leakage-current testing, I bumped an alligator clip across the capacitor terminals.  The resulting bang hurt my ears, and it now appears I will have permanent hearing impairment in my right ear.  The capacitor is rated 20mF (18mF measured), and probably had between 350 and 400V charge at the time of shorting.  (Was charged to 450V, but it had discharged some before my accident.)

I regularly wear hearing protection when running my DRSSTC or Marx generator.  Going forward I'll wear protection in many more situations.

15
Solid State Tesla Coils (SSTC) / Unconventional 3kW SSTC
« on: April 05, 2020, 05:14:17 AM »
Decided to pull out my first Tesla coil, an unconventional 3kW SSTC.  Built initially in 2013, then constructed new electronics in 2014.  Here are the basics:

3kW, 60mA RMS arc current, 50kV RMS with short breakouts, bit lower with long breakouts.
No bulk caps and no interrupter: Amplitude tracks rectified line voltage.
No primary coil.  Ferrite transformers feed 2.8kV RMS to bottom of "secondary".
160mm diameter by 600mm high "secondary" using ~1420 turns of 27AWG wire.
120 ohms DC at 20C, 75mH, 97kHz with top load.
680 x 700mm OD top-load (not quite round).
Ferrite plate layer between "secondary" and top-load.
Two H-Bridges on two 120VAC line cords, eight 16N40E FETs per bridge (16 total).
H-Bridges feed E55 ferrite transformers, 3T:35T, seconderies in series for 2.8kV RMS.
Gate-drive transformer on E55 core, eight outputs, two turns each.

The key advantage of ferrite transformers instead of primary winding is that the H-Bridges are switching at zero-crossings.  The magnetization current is small compared to the output power, unlike conventional SSTCs.

Some breakout points work much better on this coil than on my larger DRSSTC.  I think it's the high RMS arc current that helps.  These include ion-thrusters (spinners), arc coloring with metal salts, and making steel and aluminum wire into sparklers.  Here's a video link, followed by lots of pictures.  Scroll to the very bottom for schematics.
/>
Driver with dual H-Bridges:




"Secondary" showing ferrites on top:




With top load:




0.35mm diameter steel wire (stretched spring) breakout point:






Aluminum window screen breakout point:






Strontium Chloride and Ammonium Borate (soaked rags) breakout points:






Schematics:










16
Transformer (Ferrite Core) / Small DIY plasma globe using ZVS oscillator
« on: January 22, 2020, 06:21:31 AM »
This is my latest little project - only 20 watts.  Made a plasma ball from a plastic wine glass filled with about 15kPa of argon.  Works some with air at lower pressure, around 5kPa.  Experimented with argon/helium mixtures, but plain argon was the brightest.  Don't have neon nor xenon around (due to expense), the normal gasses inside plasma balls.  Mine isn't as bright and doesn't have multiple colors.  Still fun.



For the HV transformer, I used a pair of small already-potted transformers from EBay:
https://www.ebay.com/itm/20KV-high-frequency-high-voltage-transformer-ignition-coil-inverter-driver-bNWUS/323974762353?hash=item4b6e668f71:m:mg4RAb8mo-3R0Me2JUcxcfw

The pair are electrically and magnetically in series, both primary and secondary.  Magnetic path is closed with some NiZn ferrite pieces (low electrical conductivity type).  Still some gap due to the potting.  Driving circuit consists of a normal hard-switched buck converter using the same inductor as the ZVS input inductor, 19V to 15V(adjustable), with ~1.2A current limit.  Separate buck and ZVS boards, still connected with clip leads in the pictures:





The HV winding capacitance and load (plasma ball) capacitance alone makes a ~25kHz resonant frequency.  So, I added only a little bit more primary-side capacitance.  This creates an issue with the two possible resonant modes, one at ~25kHz and another (with primary and secondary voltages opposite) at ~530kHz.  To keep the ZVS oscillation from locking to 530kHz, I added a series LRC notch filter across the ZVS output (transformer primary).  Schematic is:


Here are a few waveforms of the ZVS outputs (transformer primary terminals).  First is with low load (nothing touching the plasma ball).  Second and third are with load (hand on plasma ball), showing lower voltage (due to buck-converter current limit) and a cycle or two of high-frequency mode ring at each zero-crossing.  Without the notch filter, the ZVS locks to the high frequency and stays there.




Any suggestions for improvements?

2/2020 update:  After a longer run, the little transformers developed an arc path between the two, burning through the potting material.  I've replaced them with two identical parts glued end-to-end instead, avoiding the series HV being adjacent.  Haven't ran that configuration for long yet.

17
Inspired by Phoenix' huge ferrite transformer arcs:
    https://highvoltageforum.net/index.php?topic=433.msg2609#msg2609
I decided to make a small version powered from standard US 120V outlet.  It uses a ZVS Royer oscillator directly from the rectified line voltage input, driving an 8-turn center-tapped winding on one E80 core half.  The other core half has 102 turns.  Halves joined with 0.55mm spacing for K=0.83 coupling factor.  K < 0.86 allows the oscillator to run over the full range of arc load resistance, at higher frequency under lower-impedance load.







Most of the work involved exploring how to get the ZVS oscillator to start cleanly without a huge inrush current spike, which is followed by an oscillator voltage spike due to the large energy stored in the input inductor (L4 in the following schematic).  My final solution was to bypass the power switch with a resistor R2 (actually a small incandescent light bulb).  This starts the oscillator at low power.  Once oscillating, it transitions to high power more smoothly.



Switch S1 is actually an electronic switch with isolated LV control and over-current shutdown.  Internal details of S1 aren't shown here.

Output voltage before an arc forms is +-5.5kV.  Short-circuit current (very short initial arc) is +-2.7A.  Below is a scope-capture of voltage (1kV/div with 1000x probe) and current (1A/div using 10ohm low-inductance sense resistor).  This capture is at the end of a rising arc, just as it is breaking up, where power is highest.  Second image is a zoom into the middle of the first.




To get a longer time view of arc characteristics, I switched rectified sensing.  Below are DC signals of average current and voltage.  Full-wave rectification with low-pass filtering, but no cap at the diodes (to avoid getting peak voltage).  Voltage is 450/div, or about 500V/div RMS if sine-wave is assumed.  Current is 0.5A/div average, or about 0.56A/div RMS for a sine wave.  First image is a 2-second overview, followed by two zoom-ins.





At the left voltage goes off-screen for 12ms, from turn-on until the initial arc strike.  There's much more instability in arc impedance than I'd expected, as the arc momentarily sticks to rough spots (or whatever surface characteristics make a favorable arc point).  The final arc break-up at the end of the scope capture triggers my DC input over-current limit.  Voltage doesn't drop to 0 because of the switch bypass resistor R2.

The 8ms period modulation of the current and voltage waveforms is due to rectified 60Hz line power.  The "470uF", which measures 415uF, input cap doesn't hold voltage well between line half-cycles.  That's intentional to keep power factor somewhat reasonable.  I'd initially started with just 3uF to filter HF components.  However, the arc goes out much too easily without some current flowing continuously.  Adding the 415uF DC bus capacitor made a big improvement in overall performance.

Finally, a couple videos:
/>
/>

18
Here's my first attempt at documenting a project.  It is my first DRSSTC - just complete enough to run, but with much enhancement work planned for the next couple years.  A few videos of operation, at the Portland (Oregon, USA) Mini-Maker Faire, and a couple in my back yard two weeks earlier :
   
   
   
   
   

Don't have a good assembled picture of the coil, but here's the parts:
   

Edit:  Now I do have an assembled picture:


MMC, with lots of room for planned expansion:
   

H-Bridge with 0.1mm x 100mm copper foil output leads.  E80-core current transformer is hidden under bump in output foil at right end.  Purple clip in the upper left quadrant is a crude optical probe (LED and resistor into plastic fiber) monitoring one of the high-side gate drive signals.  The pairs of TO220 FETs are the gate drives on floating 18.5V supplies, one PFET and one NFET per H-Bridge switch, driving 10 paralleled STGW60H65DRF IGBTs (hiding under the aluminum bar clamps):
   
The bulk cap array is under the H-Bridge, so not visible.  96 x "470" uF 450V.

Control circuit - in an aluminum-foil lined cardboard box at this point:
   

4-turn primary coil made of 200 strands of 27AWG wire.  Inner turn gets warm at 3kW.  Will need finer litz and/or cooling air directed that way to get 10kW eventually:
   

Bulk-cap circuit:
   

Main oscillator simulation schematic, using voltage-controlled-voltage-sources for gate drive, and FETs  for the H-Bridge because they simulate faster.  The center lower part is mostly a comparator made of discrete TO92 FETs, from M3 on the left through M10 and M11 on the right.  Nodes "vn" and "vp" are the inputs and nodes "v2" and "v3" are the true and inverted outputs.  R2, R3, R4, R7, R11, and C10 are the relevant feedback around the comparator.  No one would want to copy my comparator itself.
     

Current limit is also a bit unusual.  It is fed with a voltage-transformer (L1 and L2) from the oscillator current transformer output.  (My current transformer is 40:1 first-stage, then two 25:2 second stages.  However, one of the second stage outputs is for scoping only.)  The current limit circuit includes not only an immediate shutdown at 3500A peak (2600A in this initial version), but also simulation of the IGBT thermal transient response (C1 and C2 and associated resistors).  That way repeated long bursts will get aborted even if they don't reach 2600A.  (So far, the current limit trips only in my initial primary-only testing, not in real use so far.)
     

Finally, here's a hint of where I hope to go.  This is a sketch of a small part of what will be an array of ~500 TRIACs to switch in more primary tank capacitance as each arc grows.  My goal is to make it behave more like a QCW coil, but hopefully even better with a reverse-chirp in primary frequency to match the secondary frequency change with arc growth:
     

Before this fancy reverse-chirp attempt, I need to improve my MIDI interrupter setup, at least for next year's Maker Faire.  Also need to redo the primary tank circuit connections - going to use spade connectors instead of many paralleled 0.025" square pin connectors - that come apart too easily.  Going to explore detection of power arcs and termination of the drive enable pulse once a power arc forms.  That should make overall operation more efficient.

Hopefully I have the jpg attachments figured out now.

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