It's certainly a unique layout, I commend you for trying something new.

Thanks for the kind words, made my day

Stray inductance on your bridge output will result in voltage spikes on those outputs, the 1.6mm or so of clearance through the PCB is pretty marginal spacing and if the junction gets warm the nylon bolt will relax causing a higher impedance at the junction, causing more heating in what could result in a run away effect. How big a problem this turns out to be will depend on the final current and duty cycle, but given your bridge is potential capable of 700A, it would make me a little nervous.

This seems like a very reasonable concern. I've now removed the through hole (and thus the need for the nylon screw) from the pcb. I'll simply solder the circular crimp terminal to the pads instead (see pictures below).

In order to minimise inductance, typically you would want to run HVDC+ and HVDC- on top of one another on opposite sides of the board. This is the easiest way to minimising the loop area, encourage the magnetic fields of the current in one conductor to cancel our those travelling in the other conductor, and you have the distributed capacitance from the two planes in close proximity.

Yes I've seen many people using laminated busses for their large IGBT inverter setups although i'm sure it works for smaller inverters as well (like mine). I just couldn't figure out how to achieve this when I have to fit two other nodes (the output nodes) on the same 2-layer board while maintaining symmetry (which I've read is very important when paralleling IGBTS). With Dave's method of constructing the four copperplanes I believe the same effect can be achieved  (minimizing loop area and making sure that magnetic fields cancel each other outside the conductors) with my layout since the current paths are roughly on top of eachother. I've (very crudely) drawn the current path (it will "fan out" in reality) through the pcb:


As a side note, I'll use 2oz copper for the board.

Best of luck!

Thanks! I'll keep posting updates to this thread.

Hi again!
I think I have a plausible reason for why the right side of the bridge always fails before the left side. I remember reading about uneven leakage inductance and cross conduction on a site called thedatastream where the author (James Pawson) ran some basic simulations showcasing the effects of uneven leakage inductance in a halfbridge driving a resistive load - the TLDR is that the leakage inductance in series with the gate of the switching device introduces a phase shift to one of the gate-signals which can cause a significant amount of cross-conduction.

I ran a similar simulation (with n-mosfets) in LTspice today with a H-bridge and an LC load driven its resonant frequency. I placed 100nH in series with the gates of the mosfets in the left leg and 300nH in series with the gates of the mosfets in the right leg to reflect the fact that the wires going to the right leg of the H-bridge were ~ three times the length of the wires going to the left leg. I used this calculator to estimate the inductance of the twisted pairs https://www.eeweb.com/tools/twisted-pair/ (with D = 0.25mm and S = 1mm which gave ~8.32nH/cm).

The average power dissapated in the right mosfets were about 50% higher relative to the avg. power disappated in the left mosfets. This might explain why the right side keeps failing. Any thoughts?

Hi!
It's been a while since I last posted here but I've been working hard on my drsstc whenever possible (during summer breaks due uni-studies).
Unfortunately I've managed to get stuck and need some guidance on how to get past this roadblock. A pre-emptive apology is in place; this will be a long post.

Some basic system specs:
Driver: ud 1.3b with my own PCB (w. IC-sockets and test points):


Primary LC-circuit:
C1 = 0.2uF, L1 = 1.018uH => Fres = 353kHz
Secondary LC circuit:
C2 = 8.426pF, L2 = 24.2mH => Fres = 352kHz
(Capacitive/inductive reactance at 352kHz is 53,5kOhm)
H-bridge with IGBTs and w. TVS/zener diodes:
IKWH60N65WR6 (650Vce max)
Two 1.5KE220CA (bidirectional) TVS diodes in series across collector and emitter of each IGBT.
A 30V zener diode (P6KE30CA) across the gate and emitter of each IGBT.
Other notes:
Oversized 4700uF, 450Vdc cap + full bridge rectifier
I'm using a cascaded CT/FT setup with 14 turns on the secondaries on both cores (1 turn on the primaries). The secondary side and enclosure/heatsink is
grounded according to the scheme Mads made a while back.

The system was designed for 200A but I'm given the difficulties i'm having I would not put any faith in that number
Pictures of the system:


Equipment note: I have a variac, multimeter, oscilloscope, labsupply and a function generator at hand. I don't have access to differential probes or a proper current transformer.
I built a coilwinding machine which uses a steppermotor (I can set speed, direction and it counts the number of turns made):


I've tested the system a total of 4 times and during the latter 3 i've managed to kill both transistors in the right leg of my H-bridge (all 3 terminals have failed short).
I believe the driver works properly because it behaves as expected. To make things easier to follow/analyze i'll describe the four tests below:

Test 1 (at uni)
Here I used a helical primary and got racing sparks at a low bus voltage (see the attatched video). No IGBT failure occured during this test.
I checked the output of the GDT (without the bridge connected) by connecting the ends of 4 secondaries together (to serve as the reference)
and probed the remaining four wires with a oscilloscope like so:

(I also wanted to ask if this is a valid way of measuring the GDT output?)

The actual gate-voltage when connected to the tranistors was never checked. Here's a video of test that's hosted on my google drive:
https://drive.google.com/file/d/1FNJ4yWYNc4_DziCNGYRGblhohgXMWfLD/view?usp=sharing
I realized (after test 3) that the MMC capacitance was 0.68uF during this test (supposed to be 0.2uF) and that the gate-drive voltage during this test was horrible due
to the diode I used in parrallel to the gate resistance:


Test 2
I replaced the helical primary with a pancake primary to reduce coupling (thinking that this would solve my problems with racing sparks) and made a new secondary L.
I was still using the diode in parallel with the gate resistance during this test. The right leg of the H-bridge failed at around 90Vdc and I later found out
(when troubleshooting the system for test 4) that one string in my MMC had failed open so I was in inadvertently using the MMC at 0.45uF. I had flourescent tubes
placed in the background which lit up slightly during this test.

Test 3
I rebult the H-brige by replacing the failed IGBT's and kept the ones that had not failed short. Here I was still unaware of the MMC issue so I ran the system again,
and the bridge failed at around 90Vdc in the exact same manner (IGBT's in right leg failed; all three terminals of failed short).

Test 4
Here I figured that something more fundamental must be wrong so I did my best to find faults in the circuit before test 4. Since i'm using the Ud 1.3 driver
I was supplying the GDT with +- 24V, and due to ringing I managed to get peaks of +-32V. The waveforms in the picture is the output from the GDT measured
using the technique presented above. The secondaries were not connected to the bridge.



I replaced the 24V regulator with a 15V regulator and the waveform now has peaks at +-20V. I've read on Mads page that most IGBT's can handle more than the absoulte
max rated Vge mentioned in the datasheet (which is good since they'll turn on more) but I didn't feel like leaving this to chance once more. I also removed the diode from
gates of the IGBTs and increased the gate resistance from 4.7ohm to 8.7ohm which cleaned up the waveform nicely (here I'm measuring the actual gate voltage):



I made the driver run (without driving a current through the primary LC-circuit) by disconnecting the feedback circuitry with a jumper and then "injected" a substitue signal connected as such:



As mentioned earlier I found the MMC error here and replaced the MMC with one that has the correct capacitance (0.218uF ~ 0.2uF). I replaced all TVS and zener diodes and all IGBT's to make
sure no undetected failures would affect this test. I then conducted the test and the IGBT's in the right leg failed once more but this time at 70Vdc.
Here's the video: https://drive.google.com/file/d/1BKFW3-gKo87UF1U_2Go0uTCz-5N2gWw4/view?usp=sharing

It's hard to see but there appears to be some very small discharges occuring at the breakout point. I believe I forgot to tape the secondary wire to the ground plane during this test but I don't think it
made much of a difference. Finally, here is close up pictures of the H-bridge just before test 4 (I trippled checked that all connections were right but i'd be delighted if you can find the issue : ) ):



Comments, ideas and plan of action
I only got two spare IGBTs and they keep failing in the same manner but I cannot figure out why. Additionally it takes a suprisingly long time to fix the H-brige so I'd like to make a low inductance PCB
(somewhat similar to loneoceans Easybridge) to make replacements easier - but I need to figure out why my IGBTs keep failing before.

I've also thought about probing the Vce of the IGBTs(with low-Vbus voltage) but I've been hesistant to do so since I might damage the scope? Here's a picture of how I'd do it and
the waveforms I believe I should expect:

(I've also noticed that connecting PE (oscilloscope earth) to Vbus ground trips the RCD when Vbus voltage is applied (so it might not be possible regardless)).

I've read about IGBT latchup and thought the earlier failures could've been due to this (maybe the gate got destroyed from overvoltage while IGBT was conducting and then shoot-through occured?). If my way of measuring the Gate voltages was ok I believe the phasing was correct so I don't think this was the issue. The heatsink felt fairly warm immediately after failure but not overly hot - I could press my fingers against it without them hurting too bad. I'm at a loss as to why this keeps happening (and why the right side keeps failing - especially when the gate voltages on the right sight looks similar to the ones supplied to the left side).

I'll buy differential probes if its absoulutely neccessary but any wise advice would be greatly appreciated.

Best regards,
Jesper

I don't see any issues with the circuit, but the SN75451 is unnecessary.  NE555 output can easily drive the HFBR transmitter directly (with appropriate series resistor to limit current).

If thats the case then I'll get rid of the SN75451 and the 5V regulator. Thanks for the help!

Hi David! thanks for the thorough reply.

For UD1.3, the feedback CT has a square-wave voltage of roughly +-5.2V due to the input zener clamping.  "t" in the above equation is 1/4 cycle for a square wave and "V" is slightly over 5.2V due to winding resistance IR drop.

Why is it that "t" is only 1/4 cycle? Shouldn't it be 1/2 cycle if the dutycyle is 50%?

400:1 total ratio should be fine.  I think UD1.3 input zener diodes are 5W rated, so can handle the resulting 1A current.

So no burden resistor is used for the feedback CT?

If the current in the first stage is 20A peak I assume the first core needs thicker wire to handle the power dissapation (using cat 5 wire now). In addition to this, I was thinking of "cascading" the third core onto the first core (I only have three cores in total). Would this arrangement double the current in the primary core wires (40A)?

Hi!
How does one decide what core size to use for the feedback CT and current CT? I know that the turns-ratio is important for determining the output current (which is passed through a burden resistor of appropriate size), but how do I make sure that I don't saturate the core?

I've seen this equation which I used when constructing the GDT:

But this doesn't seem very useful in regards to the feedback/current CT since the induced voltage in the CT is dependent on the magnetic field due to the primary current. The ring cores I have are made of T38 material with a saturation flux density of 0.430mT. Their AL value is 6070nH/N^2. As of now my primary CT looks like this:

There are about 21 turns on both cores for a 1:400 reduction (I'll have 400A peak current in primary circuit). I was thinking of using a 3ohm burden resistor.

//Jesper 

Hi again!
I've been working hard on my DRSSTC but now I'm stuck with trying to understand how to build the GDTs. I've read that certain core materials are unsuitable for high frequencies (200kHz for my coil), but I haven't been able to find any equations for determining the how many turns i'll need or what core size I need to use (I suppose it has to do with the necessary inductance of the GDT?).
Any help would be appreciated!

//Jesper

Your simulation grounds the bottom of C2/C3/R1.  That is modelling a shorted GDT.

I tried using inductances to model the GDT but I didn't get it to work so I just grounded the node. I will have to try it again.

you have surmised correctly what the diode is for.
C2, C3 are to capacitively couple the GDT to avoid core walk hence saturation due to DC offset they are sufficiently high in value to make sure that no resonances are present near the operating frequency, R11 is a "Q" killer for the same reason acting as a snubber to quench ringing

That seems complicated but now I know what to google atleast. Thanks alot!

So I've been doing some searching around and found these for 4,12 euro:
Wima FKP4U031507H00KYSD

They have:

• high dv/dt = 9000V/us
• very low dissapation factor (<6*10^-4)
• 2kVdc
• Negative temperature coefficient for capacitance ==> Xc becomes larger for increasing temperature, better currentsharing?

So I think I should be able to use them in a 2S*2P configuration.

Just a quick question

How come we use the Vdc rating when selecting capacitors for the MMC? I think I'll use the 942C20P15K-F (2 parallel strings of 2 caps in series) and the datasheet states that they have a Vdc of 2kV while Vac is only 600V.

Edit: After calculating the RMS current (ontime = 200uS, BPS = 200, Ipk =500A) I get 50A, which the previous (2 parallel strings of 2 caps in series) MMC wouldn't be able to handle. I would need 4 strings of 2 capacitors in series to get the RMS-current rating up, but then I'd have too much capacitance (0.3uF instead of 0.15uF) which would mean I would need a fewer turns on my primary. I'd like to be able to run the teslacoil long enough to play music on it eventually, so I believe I have to take the RMS current rating seriously?