My DRSSTC1 rebuild / Strange GDT ringing

[LoFoTroFo]

Hello everybody.
Back in 2018 i have built my first medium sized DRSSTC.

Full-bridge:         IRGP50B60PD1
MMC:                 80nF 6kV
Fres                   165kHz
Driver :              E-bay PDM pulse skip driver

Secondary: 350x110mm with a 8x32cm topload
Primary: flat, 8-12cm inner/outer diameter tapped around 6.5 turns
OCD:  350A
Max. spark lenght 90-95cm

In 2024 i tried to tune my coil, it was a success. Without and oscilloscope i managed to achive sparks over 120cm




After this attempt my coil destroyed itself. I found that one of the OCD feedback lead broke. Soo i decided to rebuild my bridge and i wanted to change my driver. So i designed one based of the UD1.3 ... i added phase lead, and it looks like it works.



But here comes the fun part. I bought a 4ch oscilloscope and probed all 4x IGBTs G-E (no power to the bridge), and i was suprised how the gate signals looked. Btw. i do not have a signal generator so i made one using an NE555. Can somebody explain how can i suppress that ringing ? GDT is 8 turns 1:1:1:1:1 EPCOS B64290L0618X035 5400nH , gate resistors 5.1Ohm / 2W. Whats interesting that my coil worked with this GDT and gate resistors since 2018 without any problem.

Here is the photo of the signals:


And here is the output of the new driver:

[davekni]

Can somebody explain how can i suppress that ringing ? GDT is 8 turns 1:1:1:1:1 EPCOS B64290L0618X035 5400nH , gate resistors 5.1Ohm / 2W.

Vge ringing is caused by a combination of GDT leakage (parasitic) inductance with Cge (gate capacitance).  Gate resistor is to damp that ringing.  5.1 ohms is too low for your GDT/IGBT combination.
Rather than just increasing resistor values alone, I'd reduce GDT leakage inductance too.  Less inductance will allow smaller resistors so keep switching fast.  Below are links to my GDT tutorial and then Mads' recent one with video:
    https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949
    https://highvoltageforum.net/index.php?topic=3167.msg22464#msg22464
Your existing ringing is marginal.  Only real issue is first negative half-cycle after rising edges, enough to partially turn IGBT back off again.  Falling edge ring is not an issue.  Vge is below zero, and not enough negative to damage gate oxide.  Vge waveform with bus voltage applied will change too.  Was likely just good enough before.
Without diodes across gate resistors, your dead time may be marginal too.

Impressive what you accomplished before getting an oscilloscope!  You'll learn much more now being able to measure things.

[LoFoTroFo]

Can somebody explain how can i suppress that ringing ? GDT is 8 turns 1:1:1:1:1 EPCOS B64290L0618X035 5400nH , gate resistors 5.1Ohm / 2W.

Vge ringing is caused by a combination of GDT leakage (parasitic) inductance with Cge (gate capacitance).  Gate resistor is to damp that ringing.  5.1 ohms is too low for your GDT/IGBT combination.
Rather than just increasing resistor values alone, I'd reduce GDT leakage inductance too.  Less inductance will allow smaller resistors so keep switching fast.  Below are links to my GDT tutorial and then Mads' recent one with video:
    https://highvoltageforum.net/index.php?topic=1854.msg13949#msg13949
    https://highvoltageforum.net/index.php?topic=3167.msg22464#msg22464
Your existing ringing is marginal.  Only real issue is first negative half-cycle after rising edges, enough to partially turn IGBT back off again.  Falling edge ring is not an issue.  Vge is below zero, and not enough negative to damage gate oxide.  Vge waveform with bus voltage applied will change too.  Was likely just good enough before.
Without diodes across gate resistors, your dead time may be marginal too.

Impressive what you accomplished before getting an oscilloscope!  You'll learn much more now being able to measure things.

I did some tests, and here are the results: I added 5.6 Ohm resistor to the output of the driver, and it seems like that the spikes disappeared.



I connected the primary, and used a dummy load. Vbus was set to 60 VDC,  and the waveforms looked like this:


IGBT C_E


I tried to adjust phase lead too, but i got way bigger spikes with phase lead on than without the inductor .... strange ?!?



But at least the coil works.

[davekni]

I tried to adjust phase lead too, but i got way bigger spikes with phase lead on than without the inductor .... strange ?!?

How are you adding phase lead to UD1.3?  There have been discussions on the forum about doing so, but it's not simple to get phase lead that is consistent as primary current changes using UD1.3 circuitry without comparitor.

How are you measuring current?  With a third CT?  What cores are used for CTs and how many turns and what burden resistor for measurement CT?  Posting a schematic of your phase-lead-modified UD1.3 would help with any further discussion.

Vce waveform appears to show phase lead on first plot and even more phase lead (too much) on second plot.  That's likely why spikes get worse.  You may be getting phase lead due to CT inductance (on both UD1.3 feedback and on your measurement of current).  With standard UD1.3 feedback path using 74HC14 and zener clamp diodes, phase lead caused by CT inductance will decrease as primary current increases.

[LoFoTroFo]

How are you adding phase lead to UD1.3?  There have been discussions on the forum about doing so, but it's not simple to get phase lead that is consistent as primary current changes using UD1.3 circuitry without comparitor.

How are you measuring current?  With a third CT?  What cores are used for CTs and how many turns and what burden resistor for measurement CT?  Posting a schematic of your phase-lead-modified UD1.3 would help with any further discussion.

Vce waveform appears to show phase lead on first plot and even more phase lead (too much) on second plot.  That's likely why spikes get worse.  You may be getting phase lead due to CT inductance (on both UD1.3 feedback and on your measurement of current).  With standard UD1.3 feedback path using 74HC14 and zener clamp diodes, phase lead caused by CT inductance will decrease as primary current increases.

I tried to use the phase lead section of the UD 2.7c.
Here you can see the schematic for the driver.
UD 1.3 phase mod.pdf


Okay soo current was measured at feedback signal across the 51R resistor. Here im not sure if this a good idea or not, but i can measure using a separate CT.
Both the FB CT and OCD CT are 1024:1 , OCD resistor is 10R.   CT core is salvaged of a PSU



And maybe my Vce measurements are then wrong too. I measured that across the Low-side IGBT C-E. Here are more photos with different lead inductor.


purple is Vce, yellow Vge, cyan current across 51R

[Mads Barnkob]

You need at least 100 VDC on the bus, to not get fooled by switching spikes from the voltage dependant capacitances of the IGBT. The output capacitance Coes will result in virtually the same amplitude switching spikes, but they look very big against 60 VDC compared to 300-600 VDC.

Maybe your spikes are not that big afterall, but circumstances of the measurements make them look big