The evolution of a solid state Tesla coil

[Anders Mikkelsen]

Many years ago I built an SSTC, and it has been in my pile of old projects for the best part of two decades now. I recently decided to revive it using SiC transistors, to see how far I could push it, and to get a starting point for a series of planned QCW builds.

The original construction is documented on 4hv, though with some broken images: https://4hv.org/e107_plugins/forum/forum_viewtopic.php?id=42900

In the original build, I tried to go for as VTTC-like arcs as possible, inspired by Richie Burnett's examples of SSTCs running from half wave rectified mains. I was not the first to go in this direction, but this was long before QCW coils were a thing, and most documented SSTC builds had too low coupling and too low operating frequency to achieve long sword sparks.

The design itself used antenna feedback and a startup oscillator, and a full bridge of regular silicon MOSFETs. Running from halfwave rectified mains I got up to half a meter of sword sparks   This worked pretty well once I added a nice copper toroid made by Daniel Uhrenholt, and Steve even mentioned that this coil had served as part of the inspiration for his later QCW work.



There's even a youtube video of it from one of the Cambridge Teslathons, catching one of the many failures encountered by trying to push the design to the limits. In this case I had mounted the MOSFETs on a common heatsink in order to make it more portable, and the sil-pads degraded the thermal performance to the point where reliability was less than great. I decided to sacrifice the remaining transistors since I had brought the gear all the way to the UK to demonstrate it.

Since then, I've ended up designing SiC power converters for a living, and also made a phase shift full bridge induction heater using some Wolfspeed 65 mohm 1000 V SiC MOSFETs. I've had the resonator around for a while now, and decided to try to revive it using that driver. For the first experiments, I opened the phase shift control loop and set it to maximum power. As most VTTCs run with a halfwave doubler, and my MOSFETs can handle twice the mains peak voltage, I decided to feed the DC bus from a doubler running straight from mains. At first I tried open loop frequency control and got a few tens of centimeters of arcs, but it quickly became obvious that closed loop frequency control would be needed to get decent performance.

For the second run, I hooked up the PLL current transformer to the secondary base current, and got much better performance immediately. I also discovered a mostly undocumented problem as evidenced in the following video. Flashovers are not exactly a new thing, but this one turned out to have an interesting reason that I didn't find mentioned elsewhere.

At first I thought it was related to primary-secondary proximity, but deeper investigation revealed a more interesting cause. A Tesla coil resonator has multiple resonant modes, and the higher order ones are usually ignored for SSTC operation. The lowest mode corresponds with a voltage peak on the topload, and the second mode at roughly twice the frequency gives a voltage peak in the middle of the secondary. Measuring the base impedance of the coil without a topload showed all the expected modes.



The primary impedance only shows a response at two of the modes, the fundamental and twice the fundamental. This might be related to the fact that the primary covers half of the length of the secondary.



The problem seems to be rooted in the fact that adding a topload pulls the fundamental mode more than it pulls the higher order modes. When adding enough topload capacitance to represent my observed spark detuning, I noticed that the fundamental and the second mode were spaced by a frequency ratio of 3:1. Since we drive the primary with a square wave, there is strong third harmonic content, which excites this mode, causing a voltage peak in the middle of the secondary coil. I confirmed this was the cause by observing the base current at the operating point where flashovers occurred, and it was indeed mostly the 3rd harmonic of the drive frequency (spark loading damps the fundamental mode but not so much the second mode). Somehow I managed to not burn up the secondary during these experiments, mostly by luck and a quick hand on the variac.

So how do we address this? One option is to size the secondary and topload so that the second resonance is above three times that of the fundamental, by having a larger toroid for a given secondary inductance. If this mode is above three times the fundamental resonant frequency, further spark loading will only pull the modes further apart. Tweaking of the primary-secondary geometry might also help reducing coupling to this mode in favor of the fundamental. The easiest and most robust method however seemed to be a resonant primary, which greatly reduces the reflected impedance of the fundamental mode to the point where it draws much more power than the higher order modes.

So I added a resonant cap on the primary. This predictably made the coil draw a lot more current, and instead of rewinding the primary for higher impedance I hooked it up between one of the bridge outputs and ground to get the current draw back to a reasonable level. This made me lose the ability to control power by phase shift, but since I was running it mains ramped there was no issue with this. Despite now only running on two transistors, performance was greatly improved.

https://youtube.com/shorts/CSwcS3rd6PY

I got a bit carried away with the variac as is usual, and managed to blow the bridge by running it at full tilt before properly tuning the switching phase and without having OCP hooked up. Also base current feedback is less than ideal for coils with a resonant primary. The performance while it lasted, makes it evident that SiC can perform exceedingly well in mains ramped coils, and a more robust control scheme should be able to get even better results. Now it seems to do over a meter of sword sparks running non-interrupted, but I'm aiming for twice that with some refinement of the design.





So where do we go from here? The next step is to make a dedicated driver for this mains ramped coil, reducing complexity and hopefully improving performance. I'm looking at injection locked oscillators and primary current feedback, as used in some DRSSTCs where the current sense comparator is made to self-oscillate. Simulation results look very promising, and I'm planning to run some more experiments when I return from holidays. The new build will be using 30 mohm 900 V devices, as I have a practically unlimited supply of these. Voltage ratings will be cutting it a bit close when running from doubled mains, but these parts have plenty of margin (observed breakdown above 1200 V Vds). I also think it gives the devices an unfair disadvantage to run them conservatively, when most people run IGBTs well beyond datasheet ratings

[Anders Mikkelsen]

Here is an update on self oscillating comparator feedback and injection locking.

I played with a lot of ideas on paper and in simulation, with the idea to keep the whole scheme as simple as possible but not at the cost of performance. I see a lot of people are having trouble with published circuits for ramped SSTCs as evidenced by countless posts on this forum. I wanted to publish a circuit that could hopefully solve some of these issues, while proving its merits with real sparks.

As discussed in this https://highvoltageforum.net/index.php?topic=3074 thread there is a clear advantantage of using a proper comparator for this due to the well defined thresholds. I have good experience with the MCP6562 from before, and at less than 80 cents it's well worth the investment, especialy as the second comparator in the package can be used for well defined OCP behavior.

The best scheme I came up with is pictured below. It works well in simulation, oscillating at an adjustable frequency while letting the feedback signal override it when the primary starts drawing current. I'm aiming for primary current feedback here in order to guarantee ZVS/ZCS in double resonant coils, but there's no reason it can't be used with base current feeback. It should also be applicable to short pulse coils like interrupted SSTCs and DRSSTCs. There are still some advantages to PLLs for Tesla coil drive, but this gives self oscillating coils a fighting chance I think.



The implementation is basically a schmitt-trigger integrator oscillator. The oscillation amplitude is kept deliberately low to allow the primary signal to override it, limiting the amount of added phase shift imposed by the external signal pulling the operating frequency far from self-oscillation.

Phase lead is also implemented using an RC circuit. I was never a huge fan of LR phase shift due to the need for an adjustable inductor, and the inevitable magnetic field sensitivity leading to potential stray coupling between the primary coil and phase lead inductor. One clear disadvantage of RC phase lead is that it provides more phase lead as streamer loading pulls the operating frequency down, while an LR terminated current transformer does the opposite. This was solved by adding a zero, shunting the phase lead capacitor with a resistor. This allows flat or increasing phase lead with increasing frequency depending on exact values.

Then it's all down to scaling impedances and values to get everything to work together nicely, without the need for any buffering between stages. The values provided in the circuit give self oscillation adjustable from 300 to 600 kHz, and phase lead in the range of 16 - 32 degrees at 300 kHz with an 1k potentiometer. This seems about right for the application, but can be tweaked by changing component values.



I have some real test results to share, but I will save these for the next update.

[davekni]

Here is an update on self oscillating comparator feedback and injection locking.

Wonderful!  I'm a fan of self-oscillation.

Phase lead is also implemented using an RC circuit. I was never a huge fan of LR phase shift due to the need for an adjustable inductor, and the inevitable magnetic field sensitivity leading to potential stray coupling between the primary coil and phase lead inductor. One clear disadvantage of RC phase lead is that it provides more phase lead as streamer loading pulls the operating frequency down, while an LR terminated current transformer does the opposite. This was solved by adding a zero, shunting the phase lead capacitor with a resistor. This allows flat or increasing phase lead with increasing frequency depending on exact values.

Certainly agree that avoiding adjustable inductors is valuable.  I suspect ideal phase lead would be constant time, phase lead linearly proportional to frequency.  That's based on most delays through driver and IGBTs are constant time, making ideal compensation also constant time.  UD2.7 inductor phase lead is closer to constant-time than any simple RC circuit I've seen including this one, unless I'm missing something.  Gets close as impedance of node to right side of C3 approaches zero impedance.

An alternate option to consider is using fixed inductor and potentiometer.  As close to constant-time as UD2.7.  Fixed inductor can be a toroid or gapped E-core or pot-core, all less sensitive to stray magnetic fields than typical adjustable inductors are.  Shown in this post:
    https://highvoltageforum.net/index.php?topic=2054.msg15611#msg15611
As with your circuit, above version avoids a separate OCD CT.  Avoids diode temperature dependence of OCD by using schottky diode parallel clamp rather than series rectification diode.  Also responds to peak current as does UD2.7.

Mike tested this circuit:
    https://highvoltageforum.net/index.php?topic=2033.msg16893#msg16893
Not sure if any other implementations have been made.  One other poster indicated an intention to try it.

Farther up in above thread are other options, though I like this final version best.

[Anders Mikkelsen]

I had a look at other designs, but somehow missed that one as it didn't come up in my searches, and my activity on the forum was a bit sporadic in that time period. I had a look at different options for fixed inductor phase lead but was initially discouraged by the dissipation in the potentiometer or the need for a high inductance leading to potential issues with shunt capacitance. It did not occur to me to put the pot across part of the burden, which is a very elegant solution to give adjustable phase lead.

One thing that worried me with inductive phase lead, especially with the shunt capacitor on the input, is the excess gain at the resonant frequency between the phase lead inductor and the shunt capacitor. I tried simulating the proposed scheme, and it has a gain peak of 40 dB at 6.2 MHz relative to the response at the target operating frequency, potentially leading to high noise sensitivity unless I'm missing something. Removing said cap still leads to excess gain above the operating frequency, which is inevitable when you have a single zero near the operating frequency. I tried adding a pole further up to this solution, which does tame the excess gain but at the cost of phase flatness.

This was my motivation for going RC, because any transfer function realizable with RL should also be possible to get with RC according to my understanding. With inductors, RLC circuits can be made, giving complex conjugate pole pairs, but I did not find any good way to benefit from those as they imply faster phase change with frequency than circuits with just real poles.

For comparison, I plotted the amplitude, phase and phase delay of the band-limited integrator from my first post, and the tapped RL + capacitor proposed in the link, and the results are as follows:



PL2 is the proposed phase lead from this thread. PL4 and PL5 is the LR from the other thread at either end of the adjustment range. The lower pane is the phase delay in seconds, corresponding with the time of switching in relation to the time of current zero crossing. 1m of shunt inductance from the CT magnetizing inductance is also added. The circuit for reference is:



Especially the phase delay plot is very interesting, as it shows the degree of advance switching. At this point, it makes sense to try to quantify what behavior we actually want from the circuit. Phase lead is used to achieve ZVS, which is especially critical with SiC due to E_on being much larger than E_off. To successfully achieve ZVS, the load current at turn-off needs to cause the switching node voltage to commutate fully during dead-time. In other words, we need to switch before the current crosses zero, and the current at the switching instant is what allows ZVS to happen.

There is a tradeoff between the length of the dead-time and the amount of phase lead for ideal ZVS operation, but it generally makes sense to keep dead-time as small as practical in order to limit body diode conduction (for reasons of PN SiC diode Vf loss, minority carrier buildup, BPD growth). There are also propagation delays within the feedback system, which also need to be compensated for by the phase lead. This means that the amount of phase lead we need scales with the load current, since more load current will commutate the switching node faster. We can assume that higher primary current correlates with more detuning of the secondary, so if we make the phase delay diminish with decreasing operating frequency, we have a good starting point for optimal switching.

There is also the effect of bus voltage impacting the required amount of phase lead, since higher voltage leads to more charge being required to slew the switching node, but this effect is much smaller due to the highly non-linear output capacitance of the devices.

With this in mind, we can look at optimizing the circuit further. We can flatten the phase delay, and even add a positive slope to it by adding another real zero to the system. The simplest way I found to do this is to make the phase lead filter into a bridged-T topology, which looks very promising in simulation.

The circuit with preliminary values looks like this:



And the amplitude, phase and phase delay response is:



This ended up being a deeper dive than I planned, but it's an interesting topic to explore in depth. I am a bit out of my comfort zone when it comes to the theory, and I am definitely open to critique on these points.

I did implement the first RC phase lead into a prototype driver, and I was planning to document it here but this post is long enough already so I'll save it for the next one. I have still not turned up the variac all the way and the doubler voltage is sagging due to insufficient capacitance, but it still makes some sparks.

[davekni]

One thing that worried me with inductive phase lead, especially with the shunt capacitor on the input, is the excess gain at the resonant frequency between the phase lead inductor and the shunt capacitor. I tried simulating the proposed scheme, and it has a gain peak of 40 dB at 6.2 MHz relative to the response at the target operating frequency, potentially leading to high noise sensitivity unless I'm missing something. Removing said cap still leads to excess gain above the operating frequency, which is inevitable when you have a single zero near the operating frequency.

I suspect most real inductors have enough loss at 6MHz to reduce that 40dB peak noticeably.  High-frequency gain might be more concerning if it weren't for all the successful UD2.7 builds with similar peaking.  Peak frequency is likely far enough above operating range to avoid any significant excitation source.

For comparison, I plotted the amplitude, phase and phase delay of the band-limited integrator from my first post, and the tapped RL + capacitor proposed in the link, and the results are as follows:

Nice simulation.  Like your plotting of time delay.  Hadn't thought about doing that with AC simulation before.
1mH seems on the low side for CT inductance.  Delay flatness would be a bit better with higher inductance.

With this in mind, we can look at optimizing the circuit further. We can flatten the phase delay, and even add a positive slope to it by adding another real zero to the system. The simplest way I found to do this is to make the phase lead filter into a bridged-T topology, which looks very promising in simulation.

Wow, I like this topology option!  Definitely needs further exploration.  My DRSSTC from 2019 uses an LRC circuit to get roughly flat time lead over its operating frequency range.  But it has significant gain peaking not too far above operating frequency.  Been working fine for 5 years, but I'd rather avoid that gain peak.  BTW, thread for that DRSSTC:
    https://highvoltageforum.net/index.php?topic=798.msg5285#msg5285

it's an interesting topic to explore in depth.

Yes, I certainly agree.   Thank you for the exploring you have already done.

[ZakW]

Hello Anders,

Great thread, I am very interested in your work.

Regarding your last post on the circuit optimizations you made, I was hoping you wouldn't mind going into a bit more detail for me if you have time. A lot of what you and Dave are talking about is over my head and I'd really like to know more.

-Zak

[Anders Mikkelsen]

One thing that worried me with inductive phase lead, especially with the shunt capacitor on the input, is the excess gain at the resonant frequency between the phase lead inductor and the shunt capacitor. I tried simulating the proposed scheme, and it has a gain peak of 40 dB at 6.2 MHz relative to the response at the target operating frequency, potentially leading to high noise sensitivity unless I'm missing something. Removing said cap still leads to excess gain above the operating frequency, which is inevitable when you have a single zero near the operating frequency.

I suspect most real inductors have enough loss at 6MHz to reduce that 40dB peak noticeably.  High-frequency gain might be more concerning if it weren't for all the successful UD2.7 builds with similar peaking.  Peak frequency is likely far enough above operating range to avoid any significant excitation source.

For comparison, I plotted the amplitude, phase and phase delay of the band-limited integrator from my first post, and the tapped RL + capacitor proposed in the link, and the results are as follows:

Nice simulation.  Like your plotting of time delay.  Hadn't thought about doing that with AC simulation before.
1mH seems on the low side for CT inductance.  Delay flatness would be a bit better with higher inductance.

I use a small SMD transformer for the second stage, and due to their small size and low number of turns (Murata 53030C, 30:1), it only has 180 µH of magnetizing inductance which I had to account for in my phase lead design. Looking at larger toroid cores in N87, the typical 32 turn design gives around 2.5 mH which is better. Higher permeability EMI cores can push this up further as well. I agree that the UD2.7 has been built successfully many times, but I don't see a good justification for this capacitor, but a source of potential trouble.

Hello Anders,

Great thread, I am very interested in your work.

Regarding your last post on the circuit optimizations you made, I was hoping you wouldn't mind going into a bit more detail for me if you have time. A lot of what you and Dave are talking about is over my head and I'd really like to know more.

-Zak

Thanks for your interest! The idea with phase lead is to advance the feedback signal to allow switching before the current crosses zero, in order to have zero voltage switching. This is traditionally done with an LR ciruit across the current transformer, but here I am exploring other ways to do so. I'm particularly trying to get away from using inductors as they are sensitive to magnetic fields, and as a challenge. In my previous posts, I proposed an RC+R circuit that performs very similarly to the common LR circuit but without amplifying noise at high frequencies, and now also a new RC circuit that provides less variation in advance switching time with frequency. As Dave mentioned the existing circuits have been proven to work well, but I wanted to explore other options.

In order to test my first circuit, I made a PCB design for a driver using the tricks mentioned in this thread.



This board integrates the current sensing and gate drive for Silicon Carbide transistors, along with fiber-isolated interrupter input. The input section is similar to my earlier schematic, with some flip-flops added to synchronize turn-off with current zero crossing, and to latch the shutdown signal until the bus voltage falls to a safe value to re-enable the coil. I chose to use a small onboard current transformer for the second stage, and left the OCP threshold fixed. The idea is that the first stage CT is scaled to get the target OCP limit, which automatically scales the feedback signal according to the expected primary current, and also allows the OCP to protect the burden resistors from overheating.



The gate drive secion is centered a 2EDB9259Y galvanically isolated gate driver, which provides dead-time and overlap protection, and also UVLO for the gate drive power supplies. It's also compatible with 2EDF9259Y on account of the wider footprint, NCV51563 and possibly some TI and Silabs parts as well. One mistake I did was using the NCV symbol for the enable polarity, while the 2EDB has inverted polarity here. This has already been fixed in the schematic, but for a next version I'd probably add jumpers to either drive this signal from Q or /Q of U8B. Gate drive power is provided by some Mornsun DC/DCs, which are now unobtainium due to trade Sanctions, but there are parts from Murata and Recom in their place. Ylptec and Evisun have parts with the same numbers as the Mornsun DC/DCs I used, but I have tested these and I strongly recommend against using them. Teardown shows that their transformers are wound without the required isolation, and the barrier capacitance measures over 20 pF compared to the specified 3 pF for the genuine parts.



Since ramped coils need to be enabled when the bus voltage is low to reduce the chance of flashover and allow high coupling, it also includes DC bus sensing. This permits the gate driver to be re-enabled only when the bus voltage is below a few volts, which happens while the doubler capacitors are recharging. I used a circuit inspired by IGBT desaturation sensing for this. The circuit has provisions for disabling the gate drivers while the cap is charging to limit dissipation in the gate drivers, but this is largely unneccessary in my experience. To make this work I also had to add an RC delay to the startup signal, to only assert it after the disable signal has propagated.



Here is the full schematic for reference. I'm also considering posting the board files if there is interest. qa_controlboard_singleopto.pdf

I ordered these boards a few weeks ago and tested the circuit, and everything seems to work as it should (aside from the UVLO chip on the 5 V, where I had used a push-pull output chip instead of open-collector, this is also something to revisit. I threw together a quick lashup bridge using two C3M0030090K MOSFETs and powered the coil from doubled 240 V AC. Experience so far shows that the circuit starts up at the upper pole, but if the primary tank is tuned too low it will switch to lower pole operation, greatly reducing spark length. This prevents me from tuning the primary for optimal operation with spark detuning, which limits performance. This seems to be an ultimate limitation of self oscillating circuits, and while it might be possible to work around this by adding more circuitry, I will call it a day on this scheme and move on to PLL based options for further experiments. I think the project still illustrates what's possible with SiC, and I'm impressed at how long sparks can be made from two TO-247 devices with simple circuitry. That was what I set out to experiment with and in that respect I'm happy with the results.





For now the performance limitation comes from OCP tripping partway into the mains cycle when I power it from a stiff 32 A feed, with the limit at 200 A. I only ran it in shorter bursts, but even after many of these the transistors are not noticeably warm, even with a small 60 gram heatsink and no fan. I might try to retune the coil to not trip OCD, but until then I get the best results when powering it from softer mains that allows the bus voltage to sag under loading.

[Anders Mikkelsen]

I played a bit more with primary tuning and found a point where it runs close to the OCP limit when powered from a stiff 32 A feed. Bus voltage peaks at around 560 V with 8400 µF of doubler capacitance. Still no transistors blown so I have to step up my game, looks like I will have to increase the OCP limit beyond 200 A to get there. Transistors are still running cold, with the heatsink barely above room temperature after several runs, even with no fan. It looks like the die area of these parts is around 5 * 3.4 mm, and from my measurements I'm getting close to 10 kW drawn from the grid now with only two transistors powering the coil.

Here is some slow motion footage of the coil running

And it does look like I broke the six foot mark, a bit over six times the length of the secondary. Not breaking any records, but the mains ramp is a bit to fast for this arc length so branching reduces the length compared to a coil with controlled ramping. Also the secondary is a bit longer than it needs to be, but I made a point out of using the original secondary for this. Might be a new record for input power with a pair of TO-247 transistors though.

[davekni]

Great coil with impressive performance!

And it does look like I broke the six foot mark, a bit over six times the length of the secondary. Not breaking any records, but the mains ramp is a bit to fast for this arc length so branching reduces the length compared to a coil with controlled ramping. Also the secondary is a bit longer than it needs to be, but I made a point out of using the original secondary for this. Might be a new record for input power with a pair of TO-247 transistors though.

Longest arcs of a line cycle ramped coil that I've seen.  Likely a record for that.  And impressive power per FET.
QCW by "dr. kilovolt" with higher power per TO247 FET, full bridge at 35kW ramp end:
    https://highvoltageforum.net/index.php?topic=1073.0

[Anders Mikkelsen]

Great coil with impressive performance!

And it does look like I broke the six foot mark, a bit over six times the length of the secondary. Not breaking any records, but the mains ramp is a bit to fast for this arc length so branching reduces the length compared to a coil with controlled ramping. Also the secondary is a bit longer than it needs to be, but I made a point out of using the original secondary for this. Might be a new record for input power with a pair of TO-247 transistors though.

Longest arcs of a line cycle ramped coil that I've seen.  Likely a record for that.  And impressive power per FET.
QCW by "dr. kilovolt" with higher power per TO247 FET, full bridge at 35kW ramp end:
    https://highvoltageforum.net/index.php?topic=1073.0

Thanks!

As far as power goes, 10 kW is the average and not the peak. It's hard to measure exactly due to the high crest factor of the doubler input current waveform. the peak power is around 32 kW from the bridge at the peak of the burst. For comparison Jan is using four transistors and I'm using two here, and his are also 16 mohm compared to my 30 mohm ones. So I'm at around twice the power per package and almost four times the power per die area, square that for loss density, and I'm using lower Vdsmax devices and lower bus voltage. For average input power, Jan's coil is using a 3 kW PFC whereas I'm north of three times that, so a factor six per device and over eleven per 1/Rdson. This is of course because Jan is using good safety margins in his designs, while I'm not. One of my goals with this project is to explore the real limits of these devices, as has been done extensively with IGBTs in the past. Right now I'm likely not running with much margin to Tjmax, but the real question is how far beyond this we can go before there is catastrophic damage. I've been designing SiC based converters with generous margins for the better part of a decade now, and this is a refreshing change from that.

For the moment the waveforms look like this:





From detuning and current draw, it looks like the arc impedance is in the range of 16 pF + 8 kohm here as a data point.

[ZakW]

Crazy output!

Bus voltage peaks at around 560 V with 8400 µF of doubler capacitance.

Could you share your configuration for the doubler? How have you kept the ramp while boosting the input voltage?

Edit: How are you syncing the interrupter to the zero crossing as well? When I built my ramped SSTC I tried several methods and ended up using a small 120v 1:1 signal transformer for an isolated low voltage signal.

[davekni]

As far as power goes, 10 kW is the average and not the peak. It's hard to measure exactly due to the high crest factor of the doubler input current waveform. the peak power is around 32 kW from the bridge at the peak of the burst.

Makes sense.  I hadn't realized 10kW was average.  Most ramped coils I've seen skip several line cycles between each ramp.  Now I see that you are running every line cycle (every positive half+ cycle).  Definitely impressive performance!

For comparison Jan is using four transistors and I'm using two here, and his are also 16 mohm compared to my 30 mohm ones. So I'm at around twice the power per package and almost four times the power per die area, square that for loss density, and I'm using lower Vdsmax devices and lower bus voltage. For average input power, Jan's coil is using a 3 kW PFC whereas I'm north of three times that, so a factor six per device and over eleven per 1/Rdson. This is of course because Jan is using good safety margins in his designs, while I'm not.

Yes, hard to make any direct comparison.  Jan is also running phase-shift ramping, so presumably higher switching losses.

From detuning and current draw, it looks like the arc impedance is in the range of 16 pF + 8 kohm here as a data point.

Is that C in series with R, or C parallel with R?  Of course any real arc model is more complex than a single R and C.  I've always used series for simple arc models.

Transistors are still running cold, with the heatsink barely above room temperature after several runs, even with no fan.

Wow, that does seem surprising.  With the optimistic assumption that FETs are averaging 30mohms even with peak current hitting 180A and some die temperature increase, I'm estimating power at 61W per device so 122W total into your small heat sink.  Positive half of line current waveform looks to me like similar RMS to half-cycles (10ms) of 57A peak sine wave.  That would make FET RMS current 45A, four factors of 1/sqrt(2) from 180A peak.  (Peak-to-RMS of 363kHz, peak-to-RMS of line, 50% duty cycle of each FET, and 50% duty cycle of line half-cycles from above estimate of RMS current waveform)  Actual line current waveform lasts longer than 10ms half-cycle, but is also more peaked.  That's why my guess that RMS is similar to a 10ms half-sine wave.  45A on 30mohms gives 61W.  Any increase in Ron due to temperature or peak current would further increase power.  Are you driving significantly above 15Vgs to reduce Ron?

[Anders Mikkelsen]

As far as power goes, 10 kW is the average and not the peak. It's hard to measure exactly due to the high crest factor of the doubler input current waveform. the peak power is around 32 kW from the bridge at the peak of the burst.

Makes sense.  I hadn't realized 10kW was average.  Most ramped coils I've seen skip several line cycles between each ramp.  Now I see that you are running every line cycle (every positive half+ cycle).  Definitely impressive performance!

Since I'm running half-wave doubled (level shifted) mains, the coil actually draws current during the positive mains cycle, but also partway through the negative cycle. It only stops drawing current while the doubler capacitor is recharging, which takes about 4 ms for my 8400 uF doubler capacitance. It's therefore operating around 80 % of the cycle. An interesting side effect of the slow ramp down is that the arcs are very silent if OCP is not tripped, but it also costs arc length per input power since almost half the input power occurs while the output is ramping down.

For comparison Jan is using four transistors and I'm using two here, and his are also 16 mohm compared to my 30 mohm ones. So I'm at around twice the power per package and almost four times the power per die area, square that for loss density, and I'm using lower Vdsmax devices and lower bus voltage. For average input power, Jan's coil is using a 3 kW PFC whereas I'm north of three times that, so a factor six per device and over eleven per 1/Rdson. This is of course because Jan is using good safety margins in his designs, while I'm not.

Yes, hard to make any direct comparison.  Jan is also running phase-shift ramping, so presumably higher switching losses.

The losses from hard-switching during ramping is hard to quantify, but it can be significant for sure. This depends strongly on the instantaneous switch current, so it follows a sin relationship with the phase shift angle. So it strongly depends on the ramp shape and amplitude, and the additional losses approach zero when the phase shift between the half bridges reaches 180 degrees if the ramp goes all the way to maximum power. Compared to IGBTs, these losses are lower with SiC by a factor of between five and ten. I plan to experiment with phase shift ramping later, and some simulation could also go a long way towards quantifying this effect if a relistic arc model is used.

From detuning and current draw, it looks like the arc impedance is in the range of 16 pF + 8 kohm here as a data point.

Is that C in series with R, or C parallel with R?  Of course any real arc model is more complex than a single R and C.  I've always used series for simple arc models.

Series in this case.

Transistors are still running cold, with the heatsink barely above room temperature after several runs, even with no fan.

Wow, that does seem surprising.  With the optimistic assumption that FETs are averaging 30mohms even with peak current hitting 180A and some die temperature increase, I'm estimating power at 61W per device so 122W total into your small heat sink.  Positive half of line current waveform looks to me like similar RMS to half-cycles (10ms) of 57A peak sine wave.  That would make FET RMS current 45A, four factors of 1/sqrt(2) from 180A peak.  (Peak-to-RMS of 363kHz, peak-to-RMS of line, 50% duty cycle of each FET, and 50% duty cycle of line half-cycles from above estimate of RMS current waveform)  Actual line current waveform lasts longer than 10ms half-cycle, but is also more peaked.  That's why my guess that RMS is similar to a 10ms half-sine wave.  45A on 30mohms gives 61W.  Any increase in Ron due to temperature or peak current would further increase power.  Are you driving significantly above 15Vgs to reduce Ron?

That seems about right yeah. My heatsink and devices come out to around 60 J/K thermal mass, so they would be expected to rise by a couple of degrees per second. My runs so far are very short, maybe five seconds total per test for now, so the heatsink is probably some ten degrees above ambient. From testing with a fan, I can comfortably dissipate 120 W with this heatsink, so prolonged runs (minutes) are probably not too problematic, though with reduced margins compared to my short runs until now. My tests with heatsinks have shown that small heatsinks can perform very well, if the bulk metal between the fins and transistors is kept to a minimum and good air flow is used.

[Mads Barnkob]

Hi Anders

Impressive research and fun to read along something that has taken years and across two forums lifespans to develop

So how do we address this? One option is to size the secondary and topload so that the second resonance is above three times that of the fundamental, by having a larger toroid for a given secondary inductance. If this mode is above three times the fundamental resonant frequency, further spark loading will only pull the modes further apart. Tweaking of the primary-secondary geometry might also help reducing coupling to this mode in favor of the fundamental. The easiest and most robust method however seemed to be a resonant primary, which greatly reduces the reflected impedance of the fundamental mode to the point where it draws much more power than the higher order modes.

Regarding your initial post and topload size. This must be the exact reason why Steve Ward added secondary MMC, as it was practically impossible to add a larger and larger topload. I am not sure his reasoning was the same, about mid-secondary voltage profile, but as I remember it was more about sustaining enough energy to avoid it being torn completely out of tune from the long on-times.

I played a bit more with primary tuning and found a point where it runs close to the OCP limit when powered from a stiff 32 A feed. Bus voltage peaks at around 560 V with 8400 µF of doubler capacitance. Still no transistors blown so I have to step up my game, looks like I will have to increase the OCP limit beyond 200 A to get there. Transistors are still running cold, with the heatsink barely above room temperature after several runs, even with no fan. It looks like the die area of these parts is around 5 * 3.4 mm, and from my measurements I'm getting close to 10 kW drawn from the grid now with only two transistors powering the coil.

Maybe its time for a new measure of spark length / power records, to die area, instead of just device packages

[Anders Mikkelsen]

Crazy output!

Bus voltage peaks at around 560 V with 8400 µF of doubler capacitance.

Could you share your configuration for the doubler? How have you kept the ramp while boosting the input voltage?

Edit: How are you syncing the interrupter to the zero crossing as well? When I built my ramped SSTC I tried several methods and ended up using a small 120v 1:1 signal transformer for an isolated low voltage signal.

It's using a halfwave doubler like used in most VTTCs, so a capacitor in series with mains to level shift the voltage, and a diode pointing up from DC- to recharge the cap during negative half periods. This essentially shifts the entire mains waveform to be only positive. As you load it, it takes progressively more time to recharge the capacitor and the bottom of the output waveforms get clipped. This also means the peak voltage drops from 2 * sqrt(2) * Vmains. The amount of drop can be reduced by increasing the capacitors, but at the cost of higher peak currents during the negative half cycles when the caps are recharging. For now the peaks are north of 100 A with my 8400 µF, resulting in a not amazing power factor, but the simplicity vs the amount of power processed is definitely an advantage.

I have a latch to disable the bridge whenever the interrupter signal is not present, and if there is an OVP trip. Then the oscillator gets re-enabled when the DC bus voltage dips to zero, if the interrupter signal is present. This prevents it from starting oscillation whenever there is DC bus voltage present, to avoid flashovers. The circuit is using a diode to pull down a logic signal if the bus voltage is below a certain level, schematic shown in one of my previous posts. This scheme is also compatible with buck QCW operation, meaning that the enable signal doesn't have to be synchronized to the ramp generator. You can just leave the ramp generator running, and when sending interrupter pulses the driver will only enable the outputs when it's safe to do so.

Hi Anders

Impressive research and fun to read along something that has taken years and across two forums lifespans to develop

So how do we address this? One option is to size the secondary and topload so that the second resonance is above three times that of the fundamental, by having a larger toroid for a given secondary inductance. If this mode is above three times the fundamental resonant frequency, further spark loading will only pull the modes further apart. Tweaking of the primary-secondary geometry might also help reducing coupling to this mode in favor of the fundamental. The easiest and most robust method however seemed to be a resonant primary, which greatly reduces the reflected impedance of the fundamental mode to the point where it draws much more power than the higher order modes.

Regarding your initial post and topload size. This must be the exact reason why Steve Ward added secondary MMC, as it was practically impossible to add a larger and larger topload. I am not sure his reasoning was the same, about mid-secondary voltage profile, but as I remember it was more about sustaining enough energy to avoid it being torn completely out of tune from the long on-times.

I played a bit more with primary tuning and found a point where it runs close to the OCP limit when powered from a stiff 32 A feed. Bus voltage peaks at around 560 V with 8400 µF of doubler capacitance. Still no transistors blown so I have to step up my game, looks like I will have to increase the OCP limit beyond 200 A to get there. Transistors are still running cold, with the heatsink barely above room temperature after several runs, even with no fan. It looks like the die area of these parts is around 5 * 3.4 mm, and from my measurements I'm getting close to 10 kW drawn from the grid now with only two transistors powering the coil.

Maybe its time for a new measure of spark length / power records, to die area, instead of just device packages

It's nice to get back to this project, as it was what got me started in serious power electronics, and revisiting after working in this field for the better part of a decade feels very rewarding.

The wire to model arc capacitance is a neat trick, I used it as well during testing of this coil. I like the idea of adding branches to see how they affect the capacitance and ultimately the resonant frequency of the system.

I'm still curious why your mains ramped coil didn't work, as the scheme is similar to what I used here, and identical to how I used to operate the coil in the past with halfwave voltage rectification. If your devices can handle the voltage, going to a halfwave doubled scheme is nice as it gives a longer ramp and better utilizes the breakdown voltage rating of higher voltage IGBTs and SiC MOSFETs. It also doesn't draw any net DC current from mains.

I was debating whether to turn up the current limit further to see how much power the system can handle, but the fixed ramp rate is really limited how long sparks can get as there is a lot of branching. Since the optimal growth rate is fixed, and mains ramping rate is also fixed, this puts a limit on how long sparks can be grown without having branching consuming the available power. I therefore changed the plan to do controlled ramping, to see what the system is really capable of. I built a buck converter with a pair of the same FETs, and developed a ramping controller together with a friend who's much better at coding than I am. The modulator is based on an RP2040 commanding an open loop synchronous buck converter. There is no feedback, just an interrupt fired on every PWM cycle that computes a new value from basic ramp parameters. For now it's running at 58 kHz.

[ZakW]

It's using a halfwave doubler like used in most VTTCs, so a capacitor in series with mains to level shift the voltage, and a diode pointing up from DC- to recharge the cap during negative half periods. This essentially shifts the entire mains waveform to be only positive. As you load it, it takes progressively more time to recharge the capacitor and the bottom of the output waveforms get clipped. This also means the peak voltage drops from 2 * sqrt(2) * Vmains. The amount of drop can be reduced by increasing the capacitors, but at the cost of higher peak currents during the negative half cycles when the caps are recharging. For now the peaks are north of 100 A with my 8400 µF, resulting in a not amazing power factor, but the simplicity vs the amount of power processed is definitely an advantage.

I have a latch to disable the bridge whenever the interrupter signal is not present, and if there is an OVP trip. Then the oscillator gets re-enabled when the DC bus voltage dips to zero, if the interrupter signal is present. This prevents it from starting oscillation whenever there is DC bus voltage present, to avoid flashovers. The circuit is using a diode to pull down a logic signal if the bus voltage is below a certain level, schematic shown in one of my previous posts. This scheme is also compatible with buck QCW operation, meaning that the enable signal doesn't have to be synchronized to the ramp generator. You can just leave the ramp generator running, and when sending interrupter pulses the driver will only enable the outputs when it's safe to do so.

Thank you for the additional info on both points. Your method sounds easier than trying to keep everything in sync. Once I am done with my QCW project I am going to revisit my mini ramped SSTC again. But this time adding a halfwave doubler. I was able to get 21in arcs from a 2in coil running on 120vAC. I am looking forward to what I can achieve with a doubler and an improved PCB. Here is post/video if you're interested https://highvoltageforum.net/index.php?topic=2338.msg18300#msg18300.

[Daniel Uhrenholt]

Hi Anders

It’s nice to see that one of the copper toroids, I made about 17 years ago is still used today😊

It’s a nice little coil you have there!

Cheers,

Daniel Uhrenholt

[Anders Mikkelsen]

Hi Anders

It’s nice to see that one of the copper toroids, I made about 17 years ago is still used today😊

It’s a nice little coil you have there!

Cheers,

Daniel Uhrenholt

Good to hear from you Daniel! The toroid has been a nice companion of this coil since the day I received it, and it's a beautiful piece of craft. Sadly across countless moves and travels it has accumulated some dents and dings, do you have any recommendations on how to clean it up a bit? Or do you happen to have any more of these toroids that you would be willing to sell?

The buck ramping provided the expected increase in arc length and reduction in input power. I had little time to work on it due to holidays and work travel, so all the ramps are hard coded for now, running up to around 15 Hz and a peak of around 600 V on the bus, with some primary retuning done to stay within the OCP limit.



Now I'm looking into which direction to go with the project, with the aim to not directly replicate prior work by others. One very interesting avenue of research is asymmetrical PWM modulation, which would allow direct ramping from a halfbridge driver, compared to PSFB which requires a fullbridge.

I recently came across this paper which gave me a lot of hope for this method: https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/pel2.12573 . Here they also document a loss-distributive switching method for APWM which makes this method more attractive, and there's a great analysis on the degree of detuning required to maintain ZVS along with loss distribution calculation for APWM and EAPWM.

Simulation shows that APWM could be implemented with my self oscillating driver by adding a single comparator, with the reference signal taken from the timing cap of the self oscillating driver. Loss distribution between the two transistors is not perfect, but also not too bad since one transistor takes a majority of the conduction losses while the other takes the bulk of the turn-off losses, both being predominantly quadratic with current.

EAPWM is more tricky, but I have a method using a 4046 PLL and generating all the required signals for both LDPSFB, PSFB and EAPWM from the capacitor ramp signals, using a documented but not well known trick of splitting the timing capacitor into two caps with one end of each grounded, and some very simple logic.

[Anders Mikkelsen]

So let's talk about APWM.

What's APWM? Asymmetric PWM is an operating mode where the top and bottom switches have different (and complementary) duty cycles. This allows us to do ramping without having a buck converter, similar to PSFB while not needing a full bridge. So the advantage here is simplicity, a reduced parts count, less gate drivers, less transistors.

But will this allow us to switch with ZVS? To my surprise, ZVS is preserved, as long as the phase lead is increased slightly when reducing the duty cycle. The nice thing is, a self oscillating driver or PLL driver can be trivially made to track the switching edges to ensure ZVS, then the frequency will be whatever it needs for this to happen. The paper I linked in my previous post analyzes this in depth, and the required frequency shift is on the order of 1/Q, so it's something like 10 % at most, a lot less than with frequency modulation which is the other main option for ramping a half bridge coil without an upstream buck modulator.

How about ZCS? Obviously ZCS will be lost when we start switching one transistor before the current crosses zero, introducing additional losses. However, due to the asymmetric conduction period of each transistor, the opposite one in the bridge will take a larger fraction of the conduction losses, so this balances out to some extent. For the SiC parts I have been using, it looks like these losses will be pretty similar, which is really promising.

There exists a modulation scheme that perfectly balances the losses of the two transistors, by alternating which one interrupts the load current and which one takes the majority of the conduction losses on alternate cycles. The waveforms and control scheme are identical to "alternate phase shift modulation" as widely used in PSFB coils, but just using one of the bridges. The downside is that it has strong second subharmonic output for low modulation index values; when the output is turned down to zero then the output is half of the operating frequency. How this will interact with a tesla coil is yet to be explored, so due to the reasonably good loss balance of plain APWM I went with that for now.

Now how is this actually implemented? It turned out to be simpler than I expected, at least according to simulation. In my posted self-oscillating driver there is a ramp signal across the self-oscillation capacitor. If we compare the power ramp signal to this ramp, we can terminate the drive pulses early. There are some potential complications, like the ramp amplitude changing with the degree of detuning and the duty cycle of the current feedback signal changing with the bridge duty cycle, but this does not seem to be a deal breaker from simulation. LTSpice .asc file is attached with .txt extension.




I made a quick test board during a few free evenings, and sent it for production. Results to follow.

[Anders Mikkelsen]

Boards arrived this week, and after assembling them it looks like everything works. Next step is to hook it up to a resonator to see if there are sparks to be had. I shared some concept schematics with Jiří Štambera (crazyelectronics) and he managed to build and test the idea even before I received the PCBs! His test results are very promising, even using older generation Si Superjunction MOSFETs, so that's a good start.



I also had to build a proper remote modulator in order to test it, so I assembled one from scrap parts from around the workshop. It's based on an RP2040, with the code based around an example a friend wrote for me. Due to the limited number of ADCs, I'm only able to control ramp rate, ramp frequency and ramp height for now. I'll either have to add an ADC multiplexer or port it to a different platform to hook up the rest of the pots, but it will do for now.



Then I had to build a new bridge for it. I used the same C3M0030090K transistors as before, a 20 µF 1100 V film capacitor, and left some space for ceramic decoupling and RC snubbing. Since we are doing hard turn-off with this topology, it pays to be a bit careful with lead inductance and DC bus snubbing. I left the leads a bit longer than I would have preferred, but only testing will reveal if this will cause any problems.



Edit:

I had a look at the DC link impedance and tried to optimize it a bit by adding HF decoupling and damping.



Firstly we have the impedance directly across the bus planes, it shows the series resonance between the bulk cap and its lead inductance at around 230 kHz, and a nice low impedance up to a few MHz. This can be improved with a ceramic cap across the bus. A 22 nF 1000 V C0G in 1210 package was added, giving the following plot:



Now the impedance is lowered above 10 MHz, but there is a troublesome resonance at 7.5 MHz between the film cap ESL and the ceramic capacitor. Adding an RC damper can help reduce this. I didn't have a chance to try a lot of combinations, so I ended up with another 22n in series with 2 ohms. Looking at the plots, probably 1 ohm would be better but it is what it is.



And the board now looks like this: