ZCS for SSTC without E class??

[Binukrockzzz]

I was wondering if there was any way to use ZCS in a normal, non DR, non class E SSTC...

Is there any way that something like this is possible??

[AstRii]

If I understand that correctly, when the load current on the primary is much higher than the magnetizing current, the primary current will be sinusoidal (assuming the secondary current is sinusoidal). Then with some clever feedback circuitry like PLL you can set the phase of the current to be close to in-phase with the output voltage of the bridge.
You can see this phase setting on a PLL driven SSTC from Jakub Tejiščák here:
 

[AstRii]

A quick parametric LTSpice simulation confirms my statement above:

[davekni]

I was wondering if there was any way to use ZCS in a normal, non DR, non class E SSTC...

Is there any way that something like this is possible??

You can see this phase setting on a PLL driven SSTC from Jakub Tejiščák here:

Yes, a PLL is probably best way to adjust to ZCS for any given SSTC design.  Some SSTCs get lucky and hit ZCS by chance.  High coupling helps, as does a high secondary Q.  If there is just enough delay in the feedback, but not too much, ZCS can be the result.  Perhaps a feedback delay adjustment would suffice at least in some cases.

[Binukrockzzz]

Thank you AstRii and Dave for taking your time to reply to my message.

If there is just enough delay in the feedback, but not too much, ZCS can be the result.  Perhaps a feedback delay adjustment would suffice at least in some cases.

I have an adjustable RC delay in my feedback, but when I adjust it even a tiny bit, the output decreases significantly...

If I understand that correctly, when the load current on the primary is much higher than the magnetizing current, the primary current will be sinusoidal (assuming the secondary current is sinusoidal). Then with some clever feedback circuitry like PLL you can set the phase of the current to be close to in-phase with the output voltage of the bridge.

I thought about PLL, but it sounds a bit complicated to implement. I've found a circuit online for a PLL SSTC, but the diagram says 300-400khz and my planned secondary resonates at around 201 kHz (JavaTC). I want to know how to tune such a circuit to drive a lower frequency secondary... The circuit is attached below.

[AstRii]

PLL sounds complicated at first but it's actually quite simple. I recommend watching this video:

If you want the circuit to oscillate at lower frequency, you need to adjust R1 and R2. The needed values can be read off the datasheet:

Although you can just put some resistors without any thinking and simply see what frequency range does it provides. And then adjust the values.
I recommend using bigger timing capacitor because using small capacitances like <100pF leads to different center frequency every time you run the circuit..

For reference I've build two PLL coils (although without ZCS tunning):
https://www.uhvlab.org/ctu-sstc
https://www.uhvlab.org/sstc-ii

The best running PLL coil I've seen is the already mentioned Jakub Tejiščák's coil, although I've never quite understood how does his approach achieve ZCS:
https://www.vn-experimenty.eu/teslov-transformator/sstc/sstc-5.html
He is modifying the value of R2 to get ZCS, but in my understanding, R2 is there only to set the frequency range at which the PLL can operate. Somehow it works though. Maybe someone can clear this up?

[Binukrockzzz]

Thank you for recommending me that video. I now understand how a PLL works.

The best running PLL coil I've seen is the already mentioned Jakub Tejiščák's coil, although I've never quite understood how does his approach achieve ZCS:
https://www.vn-experimenty.eu/teslov-transformator/sstc/sstc-5.html
He is modifying the value of R2 to get ZCS, but in my understanding, R2 is there only to set the frequency range at which the PLL can operate. Somehow it works though. Maybe someone can clear this up?

That's the part that I dont understand too. I know how the PLL oscillates at the right frequency, but how is ZCS achieved?

[AstRii]

The best running PLL coil I've seen is the already mentioned Jakub Tejiščák's coil, although I've never quite understood how does his approach achieve ZCS:
https://www.vn-experimenty.eu/teslov-transformator/sstc/sstc-5.html
He is modifying the value of R2 to get ZCS, but in my understanding, R2 is there only to set the frequency range at which the PLL can operate. Somehow it works though. Maybe someone can clear this up?

That's the part that I dont understand too. I know how the PLL oscillates at the right frequency, but how is ZCS achieved?

Seems like this topic got buried under all the other posts, nevertheless I would like to make this question relevant again.

I have tried a few approaches to achieve ZCS with a PLL driver
1.) Adding an RC delay circuit between the pins 3 and 4 of CD4046:

(Did not change the primary current at all)

2.) Adding a delay circuit to the feedback itself:

(Also does not change the output and at certain delay, the PLL does not lock anymore)

Changing the value of R2 (pin 12) according to Jakub Tejisčák does change the phase of the primary current, but unfortunately even after contacting him, I was not able to get a response on how this works.
If anyone knows how does that work, I would very much appreciate some insight

[davekni]

I have tried a few approaches to achieve ZCS with a PLL driver
1.) Adding an RC delay circuit between the pins 3 and 4 of CD4046:

Looks like an error in that circuit.  If delay is bypassed, U4-4 (4046 output) is shorted to U3-8 (HC14 output).
Whether that works when selected (J2-1 to J2-2) depends on where driver chips are connected.  Works only if driver chips are connected to U4-4 (4046 output).

(Did not change the primary current at all)

Even if working, might not move phase enough to change primary current.  Would need to look at H-bridge voltage output relative to current to see if phase is changing towards ZCS.

2.) Adding a delay circuit to the feedback itself:
(Also does not change the output and at certain delay, the PLL does not lock anymore)

Again, need to scope H-bridge voltage and current to see phase change.  Too much delay may be preventing enough swing to trigger U1-3, or may be changing phase to the point where feedback is inverted.

Changing the value of R2 (pin 12) according to Jakub Tejisčák does change the phase of the primary current, but unfortunately even after contacting him, I was not able to get a response on how this works.
If anyone knows how does that work, I would very much appreciate some insight

Changing R2 (R14 + RV3 in your schematic) changes VCO center frequency.  That changes the VCO input voltage required to run at any given frequency.  Using phase comparitor 1, changing VCO voltage changes phase required to generate that voltage.  Expect it would be a subtle change given values you have (and values in original design linked to).

Hope above makes sense and helps.

[AstRii]

Hi Dave, thank you for the answer.

Looks like an error in that circuit.  If delay is bypassed, U4-4 (4046 output) is shorted to U3-8 (HC14 output).
Whether that works when selected (J2-1 to J2-2) depends on where driver chips are connected.  Works only if driver chips are connected to U4-4 (4046 output).

Yes you're right, there certainly is an error. Well I'm not using this circuit anymore. I'm now testing the delayed feedback circuit from my 2nd picture (with the delay circuit bypassed).

Changing R2 (R14 + RV3 in your schematic) changes VCO center frequency.  That changes the VCO input voltage required to run at any given frequency.  Using phase comparitor 1, changing VCO voltage changes phase required to generate that voltage.  Expect it would be a subtle change given values you have (and values in original design linked to).

I'm a bit confused here, I thought R1 is there to set the center VCO frequency and R2 is to set the range.

And you're right about changing R2 in my setup. It does nothing really.

However by changing R1 I can shift the output phase.

I'm running the circuit with feedback delay bypassed. Only changing the phase with R1 potentiometer. Here is H bridge voltage and primary current on the scope.

As you can see on the video, I'm a bit confused on why I'm getting the best results when the coil is not running ZCS at all.

The coil uses these MOSFETs https://cz.mouser.com/datasheet/2/196/Infineon_IPW65R041CFD7_DataSheet_v02_01_EN-1901397.pdf
1nF + 15ohm RC snubber on transistors.
2x 220nF for half bridge divider.
430kHz switching frequency
The snubber resistor on the video has 0.48Ohms resistance and only about 5nH inductance.

[davekni]

I'm a bit confused here, I thought R1 is there to set the center VCO frequency and R2 is to set the range.

If I'm understanding data sheet correctly:  With R2 infinite, R1 sets both range and center frequency.  Minimum frequency is close to zero.  Max frequency is roughly proportional to 1/R1.  Center frequency is roughly half of max frequency.  Range is roughly same as max frequency.
With finite R2, the range is offset to a higher frequency.  Range is roughly the same for a given R1 value.  R2 shifts that range higher, so shifts center frequency higher.  So both R1 and R2 affect center frequency.  R1 also changes range.  R2 affects center frequency while (roughly) keeping the frequency range constant.  So, yes, both R1 and R2 will change phase as a result of changing center frequency.

As you can see on the video, I'm a bit confused on why I'm getting the best results when the coil is not running ZCS at all.
The snubber resistor on the video has 0.48Ohms resistance and only about 5nH inductance.

Probably a bit more than 5nH just due to the length, around 1nH/mm for wires that aren't tightly paired together.  But shunt series resistance would make current waveform appear phase shifted earlier compared to reality.  Appears that current waveform is delayed relative to reality.  Perhaps scope probe and power cord ground loops explain the rest.  Looking at half-bridge output waveform in your video, it appears quite likely that actual zero current occurs before displayed current waveform reaches zero.  Ringing on half-bridge output suggests a transition to switching after zero current.
A well made current transformer may provide more accurate current measurement than a shunt, since the CT isolates scope ground.

The coil uses these MOSFETs https://cz.mouser.com/datasheet/2/196/Infineon_IPW65R041CFD7_DataSheet_v02_01_EN-1901397.pdf

Looks like a great FET.

[AstRii]

If I'm understanding data sheet correctly:  With R2 infinite, R1 sets both range and center frequency.  Minimum frequency is close to zero.  Max frequency is roughly proportional to 1/R1.  Center frequency is roughly half of max frequency.  Range is roughly same as max frequency.
With finite R2, the range is offset to a higher frequency.  Range is roughly the same for a given R1 value.  R2 shifts that range higher, so shifts center frequency higher.  So both R1 and R2 affect center frequency.  R1 also changes range.  R2 affects center frequency while (roughly) keeping the frequency range constant.  So, yes, both R1 and R2 will change phase as a result of changing center frequency.

Thank you for this explanation! Your insights teach me a lot

A well made current transformer may provide more accurate current measurement than a shunt, since the CT isolates scope ground.

I have tried a CT instead of a current shunt.
The parameters of the CT are:
turns ratio 1:20
secondary inductance: 1.04mH
burden resistor: 1.02ohm
ferrite core


However the current waveform still seems to be delayed:


If we assume the delay is exactly the time between the primary current zero crossing and half bridge voltage transition, the the delay seems to be about 241ns.

Perhaps scope probe and power cord ground loops explain the rest.

I've tried to probe the calibration 1kHz square wave with both probes at the same time to see if there is some delay between the waveforms, and there seem to be none:


I'm not sure if I can now assume that the waveform is not actually delayed and that the current really does lag the voltage. However, that would contradict a lot of what I know about ZCS.

[AstRii]

So a slight update, it seems like I was under a false impression that there will be no phase shift in a CT assuming 2*pi*f*L_secondary >> R_burden. However simulations have shown that not to be enough.
Instead of 1ohm burden resistor, I've put 0.1ohm to make it better, and the phase shift seem to still be there.

[davekni]

I have tried a CT instead of a current shunt.
The parameters of the CT are:
turns ratio 1:20
secondary inductance: 1.04mH
burden resistor: 1.02ohm
ferrite core

So a slight update, it seems like I was under a false impression that there will be no phase shift in a CT assuming 2*pi*f*L_secondary >> R_burden. However simulations have shown that not to be enough.
Instead of 1ohm burden resistor, I've put 0.1ohm to make it better, and the phase shift seem to still be there.

Should be enough.  I'm curious what simulation is indicating otherwise.  I'd guess 0.1 ohm to be less accurate.  Such low-value resistors are usually wire-wound, so have significant series inductance.  Series inductive impedance needs to be much less than burden resistance.  For your 1.04mH CT, 10 ohms or even 20 ohms should be good.  The higher voltage reduces any possible issue with scope ground voltage drop or whatever, though isolated CT output should already handle that.

If we assume the delay is exactly the time between the primary current zero crossing and half bridge voltage transition, the the delay seems to be about 241ns.

I'm now inclined to believe your current and voltage scoping is accurate.  That brings to mind another explanation.  Perhaps that 241ns delay is dead time in Vgs waveforms.  In general, optimum phase lead is such that opposite FET turns on just before (almost at) current zero crossing.  If dead time is large compared to operating frequency, that could result in FET turn-off while current is still high.

[AstRii]

Should be enough.  I'm curious what simulation is indicating otherwise.

Actually, it seems like I made a mistake somewhere, after simulating it again, 1Ohm really seems like enough.
I'm generally using Falstad online simulator for easy concepts and LTSpice for more complicated stuff.

I'm now using 15Ohm burden resistor. The phase lag seems to be the same but the waveform is much cleaner.

Perhaps that 241ns delay is dead time in Vgs waveforms.

I've measured both Vgs waveforms (without bridge voltage of course):

Assuming the FET switches when the Gate voltage reaches the Miller plateau voltage, then there seems to be about 120ns deadtime.

Here is the Gate voltage of low side FET and primary current


Here is the Gate voltage of low side FET and its Drain-Source voltage


It seems like the FET turns on before the Gate voltage reaches high enough to turn it on.

I'm starting to wish for a 4 channel scope and some differential probes

[davekni]

Assuming the FET switches when the Gate voltage reaches the Miller plateau voltage, then there seems to be about 120ns deadtime.

Looks reasonable, though the other pair of edges that you didn't zoom into shows a bit more deadtime.  Not sure why they'd be different.

Here is the Gate voltage of low side FET and primary current

Vgs does appear very early relative to current.  There's something going on that I haven't figured out yet.

It seems like the FET turns on before the Gate voltage reaches high enough to turn it on.

That is normal for proper (or excess) phase lead.  Voltage transition occurs when other FET turns off.  Remaining primary current causes the Vds transition (bridge output transition).  After transition, the FET that now has 0Vds turns on.  This is the ideal low-switching-energy situation.  Ideal when remaining primary current is barely enough to cause that Vds transition.  Not sure why yours coil seems to need such high current to transition in time.

I'm starting to wish for a 4 channel scope and some differential probes

Would be convenient, but not necessary.  Many tricks are available to get good data from two normal probes and channels.  For low voltage testing, use one probe for triggering on some stable signal such as one driver output (one GDT input).  Move other probe from one signal to the next.  (Or if possible, use external trigger input of scope on GDT input.  Then both probes are available for signals.)  For high voltage testing, connect one probe ground through a small capacitor (~5-20nF) to Vbus- and probe tip to bridge output.  Signal will have line frequency ripple on top, which will appear as random DC offset to bridge output.  For switching timing, ignore offset.  Or trigger on that signal with trigger level set to a low value such as 10V.  Then scope will capture traces only when line neutral is negative (negative diode of bridge rectifier conducting).

[AstRii]

For low voltage testing, use one probe for triggering on some stable signal such as one driver output (one GDT input).  Move other probe from one signal to the next.

That's clever. Just recently I've programmed myself an application that takes an image from the scope as the input and converts it into text file. My scope can only export images...
I've used this app and some LaTeX to render this:


Only thing I didn't capture is the high-side Gate as for some reason at the time of measurement the duty cycle was a bit off when scoping the high side Gate, making the waveform unusable for this method.

It all seems to act pretty much the way I would imagine, except the primary and secondary current.

The secondary current was scoped on the feedback CT 1:20 with 1k burden resistor
The primary current was scoped on a CT 1:20 with 15ohm burden resistor

The low side and high side Drain-Source voltage has a different peak voltage, but that's just caused the way I measured it. (turned the variac off each time I put the probe elsewhere and then turned it back on, apparently I didn't manage to set it precisely where it was before).

Edit:
Here is the picture including the high side Gate-Source. It's only usable for the first cycle, then it's skewed too much.

It's interesting to see that the high side Gate voltage looks much "cleaner"

[davekni]

Here is the picture including the high side Gate-Source. It's only usable for the first cycle, then it's skewed too much.

How are you measuring high-side signals?  The trick I suggested of using a capacitor from scope probe ground to Vbus- is good for just that, Vbus-.  Coupling scope ground to a higher frequency signal such as bridge output is usually problematic, sending high frequency current down scope ground lead.

The secondary current was scoped on the feedback CT 1:20 with 1k burden resistor

Presuming similar 1mH, 1k burden resistor will result in 20+ degrees of phase shift in measurement.

It all seems to act pretty much the way I would imagine, except the primary and secondary current.

Primary current appears to be about +-8A (+-6V) peak in these captures.  With 1nF snubbers plus Cds of FETs, perhaps the low current explains the need for so much phase lead.  At half-current point, 4A, I'm calculating bridge output transitions should take ~60ns.  But perhaps I'm missing something that makes it take even longer.  I'm used to thinking about transitions occurring at 10x higher current for normal DRSSTC H-bridges.

[AstRii]

How are you measuring high-side signals?

I used the trick where I scoped stable signal, the input to my Gate drivers. Since my driver is galvanically insulated from the bridge, I can probe high side as well.

Presuming similar 1mH, 1k burden resistor will result in 20+ degrees of phase shift in measurement.

That agrees with what we see.

At half-current point, 4A, I'm calculating bridge output transitions should take ~60ns.

How did you calculate this?

Primary current appears to be about +-8A (+-6V) peak in these captures.

Another thing that seems weird to me is that the primary current does not really rise with input voltage, at 50VDC on the bridge, it's about 6Arms and 7A at 100VDC. And even with 200VDC it does not rise above 8A. I would expect more linear behavior.

At 170V the primary current also seems like it's getting less "sinusodial", there seem to be some kind of transition after every peak. (yellow is low side Uds voltage)


Coincidentally this deformation starts happening at a voltage where the current does not seem to rise anymore.

[davekni]

I used the trick where I scoped stable signal, the input to my Gate drivers. Since my driver is galvanically insulated from the bridge, I can probe high side as well.

Presume then that scope "ground" is isolated.  Connecting probe "ground" to high frequency (fast edge) signals can still introduce measurement and even operational changes due to capacitance from scope "ground" to line.  If scoping driver too, then driver "ground" is forced to track this fast edge signal.  Capacitance through driver DC supply to line also introduces currents in "ground".  All of these "ground" currents may be fairly benign, but sometimes aren't.  However, I know of no other good way to probe high-side Vgs without differential probe.  For bridge output, I recommend measuring one at a time so scope "ground" can be at Vbus- (or Vbus+ if you prefer).  Then scope "ground" has only line frequency signal on it, low enough frequency where capacitive currents are insignificant.

How did you calculate this?

Presumed the 1nF snubbers you mentioned were on each FET, so 2nF total.  Looking at FET data sheet for 0-90Vds, average capacitance was ~250pF each, 500pF total.  So ~2.5nF on bridge output, swinging 90V, for 2.5 * 90 = 225nC charge.  Presuming a bit more stray capacitance from GDT and bridge etc, I rounded to 240nC.  240nC / 4A = 60ns.

Another thing that seems weird to me is that the primary current does not really rise with input voltage, at 50VDC on the bridge, it's about 6Arms and 7A at 100VDC. And even with 200VDC it does not rise above 8A. I would expect more linear behavior.

That's typical behavior.  Arc loading increases as voltage increases, which reduces resonant Q.  Series-resonant impedance increases as Q drops.  Simulating with different arc loading capacitances and resistances will make that clearer.

At 170V the primary current also seems like it's getting less "sinusodial", there seem to be some kind of transition after every peak. (yellow is low side Uds voltage)

Yes, low Q also results in less filtering of harmonics of square-wave drive.

[AstRii]

Presumed the 1nF snubbers you mentioned were on each FET, so 2nF total.  Looking at FET data sheet for 0-90Vds, average capacitance was ~250pF each, 500pF total.  So ~2.5nF on bridge output, swinging 90V, for 2.5 * 90 = 225nC charge.  Presuming a bit more stray capacitance from GDT and bridge etc, I rounded to 240nC.  240nC / 4A = 60ns.

Thank you, that's very straight forward

That's typical behavior.  Arc loading increases as voltage increases, which reduces resonant Q.  Series-resonant impedance increases as Q drops.

That's very interesting, I would not have guessed that the impedance increases so quickly.

Unfortunately, my transistors have gave up today when running CW mode at 1.1kW.
I've redesigned the primary coil as it was heating up quite rapidly and used 2 primaries in parallel with the same wire guage. This lead to longer primary windings and thus higher coupling and higher power.
Due to this change I was able to get very nice output for a half bridge SSTC:

Unfortunately after 1minute and 28seconds running at full power in CW mode (230V, 1450VA, 1100W) the transistors blew up.

However, I think this was caused by my over temperature protection circuit. When this happened, the heatsink was about 60C, which means the transistors were most likely not much hotter than that (80C perhaps?). Not a sufficient temperature to kill the transistor. Nonetheless around 60C is the temperature threshold at which the over temperature protection circuit trips.



This is the circuit I've been using. I've specially placed a D flip flop so that the over temperature and UVLO only trips during "zero crossing". However I'm not really sure how that worked out.
I've been able to capture what happens on the bridge during UVLO trip from previous lower power tests:



(Red = primary current, Yellow = Drain-Source of low-side FET)
The ringdown looks pretty much as what I'd expect, however the primary current suddenly floating on what appears to be another sinewave looks odd to me.

Both transistors were completely destroyed (short between G-S, short between D-S). No other parts were damaged.
There isn't any visible damage on the transistors so it's hard to say which failed first.

What are your thoughts on this and on the overtemperature/UVLO circuit?

Thanks for any replies!

[davekni]

The ringdown looks pretty much as what I'd expect, however the primary current suddenly floating on what appears to be another sinewave looks odd to me.

What are your thoughts on this and on the overtemperature/UVLO circuit?

Simulate your gating and gate drive (including GDT).  You will learn more than if I try to explain.  Then compare with UD2.X.

When this happened, the heatsink was about 60C, which means the transistors were most likely not much hotter than that (80C perhaps?).

May be circuitry as you expect.  However, die inside IGBT packages are likely hotter than 80C.  Depends on power dissipation and thermal resistance inside package and package-to-heatsink.

[AstRii]

Simulate your gating and gate drive (including GDT).  You will learn more than if I try to explain.

I find simulators very intimidating and frustrating as they rarely work for me. Either ICs are not doing what they should or the simulation breaks due to some random 100MV spike or there are some transients which make it impossible to extrapolate anything valuable.


All of this is very demotivating for me, I prefer to learn fast, that's why I'm using this forum in the first place.

However, die inside IGBT packages are likely hotter than 80C.  Depends on power dissipation and thermal resistance inside package and package-to-heatsink.

Yes, unfortunately I do not have datasheet of the heatsink or thermal pads I'm using. I can only assume the thermal resistance between the transistor pad and the heatsink is not that high, as when I've touched the transistor case and the heatsink, they felt about the same. I think I can be confident about saying that the transistors did not reach 150C to break by overheating.

Then compare with UD2.X.

From my understanding, the circuitry is the same, a D flip flop and an AND gate. However I still think my accident was caused by my UVLO/over-temperature circuitry so something I don't understand must be different.

[davekni]

I find simulators very intimidating and frustrating as they rarely work for me. Either ICs are not doing what they should or the simulation breaks due to some random 100MV spike or there are some transients which make it impossible to extrapolate anything valuable.

Yes, simulating can be frustrating.  If you plan to work in analog electronics, simulating will likely be a necessary skill.  You'll learn techniques to minimize issues.  A few key ones below:
1) Use many initial condition statements (.ic statements).  Define reasonable voltages for key nodes.  Define initial inductor currents, especially if initial voltages would cause inductor current.  Usually setting inductor currents to 0 works well.  Sometimes non-zero current is good for rapid starting of oscillators.
2) Use as simple device models as will suffice.  LTSpice provides a couple basic opamp models for example, or use a voltage controlled voltage source.  If opamp bandwidth, drive current, etc. aren't critical to circuit, use simple models.  Use built-in LVDMOS model rather than fancier models from manufacturers.  BTW, I simulate with LVDMOS FETs even if actual circuit is IGBT.  I find IGBT models are often problematic.
2a) If details are critical for one or two devices, use manufacturer models for just those devices.
3) If simulation has issues after beginning, sometimes setting smaller time step helps.  Does slow down simulation, however.  Automatic dynamic time steps are usually fine.
4) Label all nodes (wires), or at least all that are being probed.  Makes read/communicating simulation results clearer.
5) Add some realistic parasitic series and parallel resistance to inductors.  Ideal (undamped) inductors sometimes cause issues.

Your posted simulation looks reasonable, though node labels and .ic statements will help.  I can't tell what nodes are being probed (nodes 4 and 7) without labels.  Probed voltage looks odd for any pair of nodes I can think of.  Also, add a defined number of pulses so pulses train ends to simulate end of enable time.  That enable end is the issue you want to study if I understand above post.  Also, I'd add GDT input parallel snubbing to make sure GDT primary matches real circuit.

[AstRii]

Yes I've spent whole night on it, but I think I understand why the accident happens.

During the overtemperature event, the driver basically keeps the Gates floating, meaning one of the transistors will turn off slowly (through secondary GDT winding).
If the transistor don't switch off quick enough (before the primary current starts another cycle), the transistor will suffer heavy loss and will fail.

I've solved this problem by using another winding on the GDT, that shorts the transformer to GND, eliminating any residual charge on the transistors.



I'm not sure how this will work in practice and I still can't wrap my head around why an UD2.7C driver does not need such feature, to me the GDT drive circuit looks the same.

[davekni]

I'm not sure how this will work in practice and I still can't wrap my head around why an UD2.7C driver does not need such feature, to me the GDT drive circuit looks the same.

They are not the same.  The difference is why you are having issues.  There can be a small residual GDT signal after UD2.7 disable.  There are posts on the forum showing GDT traces at the end of enable.  Generally residual gate voltage is below IGBT threshold.  Your clamp would help clean that up.  However, it is a klude to fix a basic gating issue with a clamp.

[AstRii]

They are not the same.  The difference is why you are having issues.

I think I understand the issue now. The difference is that my current driver after the falling edge of enable will have one gate driver outputting high and other gate driver outputting low. This means there will be full input voltage across the GDT primary (not causing a short circuit thanks to the DC blocking capacitor). This also means that the secondaries of GDT will have nowhere to discharge.

However UD2.7 gate drivers will both output the same logic state (high) after the falling edge of enable.
This shorts GDT secondaries through the gate driver's high side PMOS through the voltage source it's being powered from to GND. Removing any charge from the Gates of power transistors.

Did I get that right?

Unfortunately I was in a rush to order new PCB as this coil needs to be finished soon. So the new driver PCB will use the "clamp" winding.


I will use UD2.7 output stage in the next iteration or perhaps even galvanically insulated Gate driver ICs. 

[davekni]

I think I understand the issue now. The difference is that my current driver after the falling edge of enable will have one gate driver outputting high and other gate driver outputting low. This means there will be full input voltage across the GDT primary (not causing a short circuit thanks to the DC blocking capacitor). This also means that the secondaries of GDT will have nowhere to discharge.

However UD2.7 gate drivers will both output the same logic state (high) after the falling edge of enable.
This shorts GDT secondaries through the gate driver's high side PMOS through the voltage source it's being powered from to GND. Removing any charge from the Gates of power transistors.

Did I get that right?

Yes, with one tiny change.  UD2.7 gate drivers output high, so low side NMOS FETs are on.  Otherwise exactly correct.

Unfortunately I was in a rush to order new PCB as this coil needs to be finished soon. So the new driver PCB will use the "clamp" winding.

Clamp solution does leave one issue unresolved:  The DC blocking capacitor starts charged rather than at 0V.  Given lower IGBT current at start of enable, this start condition issue MIGHT not cause failures.

At the risk of providing too much information:  Your boards are trivial to patch.  Just use the driver chip enable pins instead of AND gate on input.  UD2.7 avoids using enable because that would leave driver chip outputs low.  Low driver outputs would turn on PMOS outputs, except that PMOS gate drive is AC-coupled.

[AstRii]

Yes, with one tiny change.  UD2.7 gate drivers output high, so low side NMOS FETs are on.  Otherwise exactly correct.

Thanks a lot for the confirmation

The DC blocking capacitor starts charged rather than at 0V.

Wouldn't a discharging resistor parallel to the cap solve this issue?

Just use the driver chip enable pins instead of AND gate on input.

I have thought of that, however IXDN6XX / IXDI6XX drivers do not use the enable pin. There is a IXDD6XX version of the non inverting driver that uses it, however there is no such option for the inverting chip. Also the IXDD6XX chip outputs High-Z instead of low when enable is low, that is not much helpful. I've picked these drivers a long time ago since they are in a TO220 package so they are easy to cool and they are not much costly, however now I see they are not the best in this situation.

[davekni]

Wouldn't a discharging resistor parallel to the cap solve this issue?

A resistor might help a little with how fast cap discharges after enable starts.  Doesn't fix issue.  Mostly wastes power and starts GDT primary with some DC current.

I have thought of that, however IXDN6XX / IXDI6XX drivers do not use the enable pin. There is a IXDD6XX version of the non inverting driver that uses it, however there is no such option for the inverting chip. Also the IXDD6XX chip outputs High-Z instead of low when enable is low, that is not much helpful. I've picked these drivers a long time ago since they are in a TO220 package so they are easy to cool and they are not much costly, however now I see they are not the best in this situation.

OK, makes sense.  I'd looked at your schematic symbol and not at part data sheet.  Unusual to have high-Z as the disabled state.  If the chip version you were using had enable, high-Z combined with your clamp and some resistance across DC coupling cap would fix everything.

[AstRii]

Actually what I forgot to mention is that I also changed the IXDN609 for IXDD609 and routed the Enable pulse to its enable pin. It's funny because I did this change without simulating it or thinking about it, as I said I was in quite a hurry to order new PCB and I had just an intuition that this change will help.

If the chip version you were using had enable, high-Z combined with your clamp and some resistance across DC coupling cap would fix everything.

I'm so glad to hear this confirmation. Thanks a lot. I will keep you updated when the new PCB arrives