Self Oscillating Half Bridge Wonder

[Acid Byte]

Actually continued on the schematic and add another extra resonator.
also went upto 200vdc as of today.
starts to become funny.
but start to need beter capacitors as run time is fairly short due to heat up of the capacitors
Second video is with only a single resonator in place

[Magneticitist]

200V nice!

[kyledellaquila]

Wow! Thank you for sharing your thoughts and progress with this design. Very impressive performance in the last video you just shared. The breakout starts without assistance from a sharp point

I can see what you mean by the capacitors heating up.. looks like the package had it! You need capacitors with heatsinks attached.

Do the FETs get toasty too? Have you considered running them in parallel in this design?

Is inductor L1 for current limiting?

You mention that L2 inductor requires delicate tuning. I assume that L1 and C2 represent are the resonating circuit that you would have to match with L3?
How do you go about specifying the values?

I assume for your dual resonator that each end attaches to each end of the L2

[Acid Byte]

Wow! Thank you for sharing your thoughts and progress with this design. Very impressive performance in the last video you just shared. The breakout starts without assistance from a sharp point

Your welcome, i liked the design and thought i would give it a try.
At the moment im on 240 vdc and think i can increase it even more with some cooling on the heatsink.

I have added a L3 open coil to the design at 1 end of the L1 coil to get this flame (the circuit has to be tuned for coil L3 for iit to work)

I can see what you mean by the capacitors heating up.. looks like the package had it! You need capacitors with heatsinks attached.

heheheh i just need better capacitors that's it.
on my single switch version i had a 4x4 150pf cap bank.
i probably should get something similar ( but a little stronger) for this halfbridge design taking the input voltage increase into perspective.

Do the FETs get toasty too? Have you considered running them in parallel in this design?

The fets do get a little warm but that takes a considerably long time,
nothing that cant be cooled down with a fan on the heatsink

Is inductor L1 for current limiting?

In my circuit L1 is indeed for current limitting
Inductor L2 is for current limitting in the half bridge schematic ( the 100uH coil )

You mention that L2 inductor requires delicate tuning. I assume that L1 and C2 represent are the resonating circuit that you would have to match with L3?

Like L2 on my circuit requires the delicate tuning so does L1 on the halfbridge schematic.
On my circuit L2 and C1 make up for the resonant circuit
Like on the halfbridge L1 + C5 + C6 make up for the resonant circuit
Both case they have to be tuned to match the external resonator indeed ( in my circuit that is L3 )

How do you go about specifying the values?

As i honestly dont know how to calculate them i ussually find the "correct values" by trial and error.
i do try to get it in the ballpark with a inductive reactance calculation of coil L2 (on my circuit) and find a capacitor suitable to match frequency on the resonator.
you basicly dont want to kill to much current passing it to the resonator,
but have to take into consideration that to much current could potentially pull to hard on the mosfets gate.

I assume for your dual resonator that each end attaches to each end of the L2

The dual resonator was done on the halfbridge circuit of this post and its 1 resonator on each side of L1
But seems to no work that great, considering the much bigger arc i got from the single resonator on halfbridge.

[kyledellaquila]

https://youtu.be/-AQmaAEyTic
Looks like Teslaundmehr published a new video detailing a similar schematic as you have shared Acidbyte.


I appreciate the high efficiency zero switching nature of this approach. While this all enables smaller and smaller high-frequency and high-throughput designs, I would love to take the learnings here and scale this up to lower frequency larger coils + higher throughput. Perhaps going in the direction of an H-Bridge and/or parallel MOSFETs.

And the final cherry on top would be to modulate this with audio input to produce QCW saw-tooth effects etc. (my best guess at doing that would be to place a linear MOSFET and associated linear op-amp driver where that potentiometer is located for full modulation control.)

It would be nice to have complete control over the modulation while still being a simple add-on. In order to control (1) signal bias for the gate of the output MOSFET, and (2) the volume level of the modulation signal. [as shown below]. I am no op-amp expert so I am not 100% sure how to do this in the most minimal way possible.

[Magneticitist]

I think this forum needs a section for these now. Plus Steve Ward has demonstrated a single fet circuit which my mind is still having trouble rationalizing.

[kyledellaquila]

Wow! Unbelievable performance that Steve has got there... Thanks for the note @Magneticitist
https://youtu.be/s3rRKujv0UU
Sounds like SiC enabled some serious performance.
Now we just need to get some amplitude modulation going on here.

[Steve Ward]

Sounds like SiC enabled some serious performance.

I got very similar performance with a FDH44N50 Si MOSFET, so it's not just "use SiC and you'll get huge arcs".  I recommend learning on low cost Si, like IRFP460, before trying SiC.  I have a few P460A's in my collection, so maybe i'll demo what can be done with that fet sometime, but i think 6" flame is probably well within range.  I would not waste time with lower voltage devices, save the P260N's for a bus modulator or something useful ;-).

The real performance enhancement is in the tuning, my setup runs almost constant primary current over the range of 20-120V input with slightly declining primary current at higher input voltage (i've gone to 140V so far, but loss of ZVS was becoming apparent). 

Previous secondary coils which had more inductance and capacitance had required about double the primary current to reach similar flame size, and then i realized its probably better to just minimize Csec as much as possible, and that double resonance isn't required for such a low voltage machine.  Instead, the output coil just provides voltage gain via induction, and with its Fres being significantly higher than operating freq, there is not much phase shift between primary voltage and secondary output, so primary voltage directly contributes.

I do most of my tuning exploration in ltspice before trying on the real thing, though i have to use the real thing to capture the plasma loading effect to run a realistc sim, so its an iterative process.  Max power level so far was around 1 to 1.2kW, but it looks like it could do 1500W with the 650V fet i have now, and ~3kW with 1200V, and *much care* given to the tuning.  It's a fine balancing act, but fortunately with this "detuned" approach the plasma load seems to nicely match the class-E requirements over a wide operating range, enabling the self-oscillator to run reliably at high power.

In fact, since using the de-tuned approach i have not lost a single FET, even when pushing the drain voltage beyond device spec by some 25V-50V.  And for those wondering, yes, i did break a few (4) SiC devices, i believe each time caused by loss of ZVS due to mode-hopping when the flame became too big, or simply overloading them thermally, as the old secondary ran with double the primary current!

I'm writing a paper that details the theory and design of my HFSSTC and the various ways I worked to optimize it, hope to publish it to a new website within the next weeks.

[Andrew321]

I have a really basic question about all this. In Acid Bytes schematic, what is the purpose of C2? Is it to increase gate capacitance? Why would this be needed?

[Magneticitist]

All you guys who share this research are awesome and it's really appreciated. Highly awaiting the details of this setup.

[kyledellaquila]

@Steve Ward – Hi Steve, I am happy to see that you found this thread! I was planning on reaching out to you on your youtube page comments but didn't get around to doing it. Thank you for sharing your initial thoughts here on this thread. I learn something new every day. Very excited to see your notes on wrangling such a strange circuit beast (as well as your new website!).

I have a really basic question about all this. In Acid Bytes schematic, what is the purpose of C2? Is it to increase gate capacitance? Why would this be needed?

By "de-tunned", is the output coil f-res (significantly) higher in frequency to assure no mutual resonance back into the primary? I imagine that could be a sure way to wreck any delicate MOSFET.

I have a really basic question about all this. In Acid Bytes schematic, what is the purpose of C2? Is it to increase gate capacitance? Why would this be needed?

Hi @Andrew321 – I was wondering the same thing. I was visualizing the oscillation path of C1 & L2 and found that the path of least resistance to ground is through C2. And then I started thinking about how hard the Zener / TVS diodes must be working to protect the gate until I noted the difference in capacitance between C2 and C1. I believe what is going on here is that C1 & C2 represent a "capacitive voltage divider" where C1 is 150pf and C2 is 4700pf – which should step down the voltage at the gate to 3% of what C1 sees. I highlighted the return path in light green below:

[Andrew321]

Hey Kyledellaquila, thanks for the reply. I was thinking it might be something like that because if it out puts in the KV range what's to stop the gate from being over voltaged except TVS diodes? I don't imaging they would last too long under more continuous use. So then when voltage is applied current flows through resonant coil to the resonant capacitor and the path to grounds is formed via the  external gate capacitor. When the mosfet turns on, the charges stored in the capacitors would flow in the revers direction and through the mosfet back to ground. then the mosfet turns off and the cycle repeats. is that about right? And the First coil (I think the RF choke) limits current when the mosfet turns on so it doesn't become a dead short. I just got an oscilloscope in the mail a could days ago and I'm very excited to test things out! 

[kyledellaquila]

Hey Andrew, your description sounds right. I hope your build works out! I have yet to construct my own (missing parts in the mail)..
This got me thinking though.. I wanted to know more about the differences between the 1st, 2nd compared to 3rd schematic I have shown above.
So I started to decimate the 3rd schematic to better represent the single MOSFET arrangements of the 1st and 2nd: https://tinyurl.com/y9sy2tkr
One major difference I noted was the usage of a capacitors on each side of the working coil.
In schematic 1 & 2 (provided by Teslaundmehr & Acid Byte) a capacitance linking to ground is not present. I have shown the position of this capacitor in the diagram below in the dashed lines:

https://tinyurl.com/yd5dpqyy
The interesting thing is that I was unable to get schematics 1 & 2 to work in my Falsdad simulator if constructed as described in the original schematics. Once I introduce a capacitance on the other side of the working coil, I was able to get the circuit to oscillate.
The diagram below has the main oscillation path highlighted


Without that capacitor, I was unable to get the Falsdad simulation to socialite properly. Is this an artifact of Falsdad simulator? Can anyone else confirm this?

Also three extra notes:
(1) A diode at the MOSFET Source pointing towards ground (disabling the MOSFET body diode) seems to improve performance. (No disharmonious ringing)
(2) What are the dangers of putting more MOSFETs in parallel in this scenario? https://tinyurl.com/y7vy2tht This pseudo diode free ZVS driving method should make for parallel operation hassle free no? (for higher power purposes)
(3) What is the most simplistic way to AM modulate this circuit (with as few steps as possible)?

[davekni]

Youtube's suggested-video list came up with this Russian HFVTTC at 18MHz and 21kW, making 1m long "flames":

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A bit of google-translate on the comments shows that he is using a breakout made of carbon-fiber cloth and sodium-chloride, thus the bright yellow "flame".

[kyledellaquila]

Incredible what they are able to achieve out there!
I am so curious to see what people's high-reliability set ups are..
Thank you for sharing!

[madhurya]

Hi all!
Fascinated by Laphicets circuit mentioned in the OP, I have been trying to simulate it in LTSpice, but in vain so far. Looks like you guys have it all figured out, so I figured I'll ask here, with hopes that someone would point out my mistake(s).

Here is what I have so far: https://imgur.com/a/nwtyiv3

The simulation runs, but does not resonate. Voltage across L1 oscillates between +-110V at 50Hz, same as input and not the expected >10MHz as per Laphicet.

As is obvious, I've had to make a coule pf minor tweaks for components which are available in LTSpice. I figure those tweaks are not the cause of lack of oscillation, but I could be wrong.

I'd happily share my schematic file with anyone willing to look at it first hand.

Disclaimer: Before you experts prepare your brick bats, please be gentle! I'm a relative newbie in circuit design and LTSpice, but hope to learn quickly.

[davekni]

Voltage across L1 oscillates between +-110V at 50Hz, same as input and not the expected >10MHz as per Laphicet.

AC input voltage isn't listed on schematic.  Are you applying 110V or 220V?  Initial circuit used 220V RMS.  That is +-311V peaks.  Spice sine voltage sources are specified by peak amplitude.
Results will be easier to measure if you move ground connection from AC input V1 to negative supply node (source of Q2 etc.).  Even though real use may be with a ground-referenced AC line input, moving ground will not effect simulation.

[madhurya]

Voltage across L1 oscillates between +-110V at 50Hz, same as input and not the expected >10MHz as per Laphicet.

AC input voltage isn't listed on schematic.  Are you applying 110V or 220V?  Initial circuit used 220V RMS.  That is +-311V peaks.  Spice sine voltage sources are specified by peak amplitude.
Results will be easier to measure if you move ground connection from AC input V1 to negative supply node (source of Q2 etc.).  Even though real use may be with a ground-referenced AC line input, moving ground will not effect simulation.

Thank you David for your prompt response and apologies for the delayed reply (the notification email went to spam )

AC input voltage was setup as 220VAC 50Hz SINE, which was a mistake as you pointed out. I corrected it to 311V amplitude and ran the simulation again. Amplitude of voltage across L1 did change to +-153V but frequency remained at 50Hz unfortunately. Same result for moving the ground. i.e. Still no resonance.

I remember hearing/reading somewhere that resonance in these types of circuits depends on the fact that "no two MOSFETs are identical and one switches on before the other, triggerring the resonance".

Could the problem in my LTSpice simulation be that the simulation is too perfect? i.e. Both MOSFETs are perfectly synchronized, which will never happen in practice? If this could be the case, how may I "fix" this too perfect simulation? Laphicet mentions that he has been able to simulate this circuit up to 30MHz. I wonder how he achieved that? His diagram appears to have been designed in LTSpice, so I figure I am using the correct tool.

David, may I ask what tool did you simulate this circuit in? And would it be too much to ask if you could share your schematic with me to use as a reference? What voltage do you see across C3, C4, C5 and C6? Looking at the falstad simulation @kyledellaquila linked to, I see that voltage across those capacitors never goes beyond +-150V.
I ask because I am having a hard time finding 68 pF ceramic capacitors rated at 10kV or higher. Closest I could find was one rated at 4 kV. I wonder if it would be OK to use those instead?

[davekni]

Could the problem in my LTSpice simulation be that the simulation is too perfect? i.e. Both MOSFETs are perfectly synchronized, which will never happen in practice? If this could be the case, how may I "fix" this too perfect simulation? Laphicet mentions that he has been able to simulate this circuit up to 30MHz. I wonder how he achieved that? His diagram appears to have been designed in LTSpice, so I figure I am using the correct tool.

Yes, LTSpice is my favorite analog simulation tool.  And perfect balance is sometimes an issue.

David, may I ask what tool did you simulate this circuit in? And would it be too much to ask if you could share your schematic with me to use as a reference?

Here's my schematic with the latest version of values.  Took me a bit to find it from 2+ years ago.  Didn't save the many iterations.  This version has FET parts I have around, but that is easy to change.  (I never tried building this.)  ".ic" directives in upper left are to fix the startup issue.

What voltage do you see across C3, C4, C5 and C6?

In the above version with 300Vdc input, 2.3kV peak.

I ask because I am having a hard time finding 68 pF ceramic capacitors rated at 10kV or higher. Closest I could find was one rated at 4 kV. I wonder if it would be OK to use those instead?

Probably fine.  Current rating (or voltage at high frequency) may be the limiting factor.
Series-connect string of lower-voltage caps is another option.

[madhurya]

Thank you very much @David for this valuable information. This will keep me busy for a while .
I appreciate you taking time to dig through your archives!