Super flat QCW simulation (does this look reasonable?)

[toooldforthis]

Hello, I want to build a super flat QCW coil to fit into a fake book. I'm wondering if my simulation and tunings look reasonable to folks here? The primary is Litz and the secondary will be a 200mm OD flat PCB coil with C0G ceramic caps soldered on the back side to make a secondary resonant tank. I simulated in both the time domain and the frequency domain. I'd like to get secondary impedance higher but I can't physically make the coil any finer on the PCB. I'm running at the lower pole in this simulation as you can see. Any obvious issues before I order boards?

[toooldforthis]

Here's my continued work on this project (really just documenting it so I don't forget my thinking lol...)

I re-tuned the resonant tanks and decided to switch to the high pole and use a PLL to lock to the high pole. It seems like using a PSFB tends to force the higher pole anyway - I guess due to more energy being present at higher harmonics during low duty cycles. The secondary will now be a flat 250mm spiral using the top and bottom of a PCB to get the resistance lower. My secondary impedance will still be a good deal lower than it would be had I designed with a normal cylindrical winding as everyone else uses. We will see if this causes problems. I'm hopeful it just results in higher secondary losses due to the higher current as well as less streamer detuning.

I simulated this thing and seem to have soft switching on both legs of the bridge? I thought this was not possible? Spice file attached. Currently using CoolMOS C7 as Quorvo models don't want to converge.

I'm about to order the board I think.

[davekni]

I simulated this thing and seem to have soft switching on both legs of the bridge? I thought this was not possible?

Yes, it is possible and desirable.  With correct dead time phasing, one FET turns off, remaining (small) primary current causes Vds to rise, then opposite FET turns on as its Vds approaches 0V.

Currently using CoolMOS C7 as Quorvo models don't want to converge.

Yes, some models have trouble converging, especially IGBT models.  Often the old LTSpice IV converges much better than any version since then.  I use LTSpice IV most of the time.  Haven't found any advantage to newer releases.

[toooldforthis]

Well the driver board seems to work and the PFC has been designed but not yet ordered. I wrote code for a "WIO Terminal" to output 200kHz PWM that gets low pass filtered into the ramp. The board produces variable phase offsets between its two inputs as you can see in the scope shots below.

I'm using a signal generator to provide a 400kHz reference ATM.