Author Topic: Idea for QCW DRSSTC  (Read 844 times)

Offline AstRii

  • High Voltage Technician
  • ***
  • Posts: 146
  • Karma: +4/-0
  • Czech Technical University in Prague
    • View Profile
    • UHVlab - Tesla Coils | High Voltage | Education
Idea for QCW DRSSTC
« on: September 19, 2021, 07:58:09 PM »
Hello guys,

Lately there have been quite a few topics about phase lock loop implemented with 4046 chip and it got me thinking..
In QCW DRSSTCs we either ramp the voltage (current) in the primary by using ramped output of a DC-DC buck converter or we phase-shift the two halves of the full bridge and then shift it back during the pulse.
I have never built QCW DRSSTC before so I can't imagine how hard it is to implement the phase-shift modulation but I can imagine that building a high power DC-DC buck converter is a though work.

I thought about another approach with 4046. We can lock the PLL to the resonant frequency of the primary at the start of the pulse and then send a ramped signal to the pin 9 of the 4046, forcing the VCO to oscillate at slightly different frequency.
This ramp signal would be "inverted" as we start at the highest voltage and then go to 0V at the end of the pulse (or probably sooner). This way we lock the PLL to the correct frequency, then we force it to oscillate just slightly off and as we go further into the pulse we are getting closer and closer to the correct frequency at which the impedance of the primary circuit will be the lowest. This "frequency shift modulation" should regulate the primary current and ramp it.

The only problem I see with this design is that we would need the PLL to lock on the primary resonant frequency even before we send any current to the primary, but I'm sure there will be some easy workaround circuit for that.
Do you guys see any obvious problems with the technique?

Thanks for any replies!
- Mark
Marek Novotny
Czech Republic, Czech Technical University in Prague
www.uhvlab.org

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #1 on: September 19, 2021, 08:28:05 PM »
The only QCW coil I've made so far was my low-frequency experiment (100kHz) with a separate buck-converter stage.  I am planning a more conventional 350-450kHz QCW coil using phase shift with FPGA control (digital PLL).  Goal is to experiment with conventional phase-shift vs. pulse-skip (which is speculated to not work) and audio modulation.

However, I'm not entirely sure exactly what others mean by phase-shift when applied to QCW.  My plan is to shift relative phase of the two H-bridge halves, which becomes duty-cycle modulation to the primary.  That is my guess as to what others do too.  Perhaps instead some designs shift the entire H-bridge voltage phase relative to primary current, which results in a small frequency shift.

It is theoretically possible to ramp a QCW coil entirely with an appropriate open-loop frequency ramp.  Would be hard to get the ramp shape just right, but you may be able to get reasonable results.  That would be a fascinating experiment!  I love trying non-conventional approaches.  Many fail (like my low-frequency QCW), but trying leads to learning and sometimes invention.  If you proceed this way, I see no reason to lock first.  You want to start farther from resonance and ramp towards resonance.  You could use just the VCO and ignore both phase comparitors.  Or, you could switch in a phase comparitor near the end of the ramp to optimize final phase for max power.

The alternative that comes to mind is to use the 4046 as a PLL with a ramped current source added to the VCO pin to force a phase offset.  Likely best with phase comparitor 2 to allow 90-degree shift.  Of course, current source needs to ramp towards 0.  Adjusting initial current to get almost 90 degrees might be finicky.

Good luck!

PS:  Thinking more about open-loop frequency drive for a QCW coil.  Seems possible that it could provide better ramp control, causing the arc to grow based on arc loading.  Seems it should work best on a coil with high coupling and primary tuned below secondary, maximizing frequency shift with arc load.
David Knierim

Offline AstRii

  • High Voltage Technician
  • ***
  • Posts: 146
  • Karma: +4/-0
  • Czech Technical University in Prague
    • View Profile
    • UHVlab - Tesla Coils | High Voltage | Education
Re: Idea for QCW DRSSTC
« Reply #2 on: September 19, 2021, 09:47:14 PM »
I am planning a more conventional 350-450kHz QCW coil using phase shift with FPGA control (digital PLL). 

That's the beauty of this design, you should not need any FPGA or microprocessor (well maybe except generating the ramp signal).

If you proceed this way, I see no reason to lock first.  You want to start farther from resonance and ramp towards resonance. 

I'm not sure if I follow.. You need the PLL to lock at the resonant frequency of the primary so that the ramp will be closer and closer to the resonant frequency.
Without locking to the primary resonant frequency through a feedback transformer (as usual in DRSSTCs) the frequency which you are getting closer and closer through the pulse would not necessarily be the resonant frequency.
In an SSTC the 4046 starts slightly off and then through feedback it locks on the secondary resonant frequency. I'm thinking of the same idea.. let the 4046 generate a signal which would be quite close to the primary resonance, then wait before it locks to the correct resonant frequency of the primary and then use the "ramp" signal to force it off and slowly getting back. The problem is that it can take even a few milliseconds before the PLL locks. If we'd run current through primary coil during this time, it would already be too high before 4046 even locks.

Good luck!

Thanks a lot Dave, unfortunately I'm quite busy right now building my SSTC II, coilgun and the school starting again. But once I'll have the time for it I will definitely try to build such a coil (if somebody doesn't disprove the idea beforehand).
Marek Novotny
Czech Republic, Czech Technical University in Prague
www.uhvlab.org

Offline johnnyzoo

  • High Voltage Enthusiast
  • *
  • Posts: 27
  • Karma: +1/-0
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #3 on: September 19, 2021, 11:09:37 PM »
Not a Tesla coil expert here so take this with a grain of salt, but just some thinking...

Buck converter seems like a "brute force" solution, bulky, plenty of extra components, but probably robust when done properly, and the design is somewhat straightforward.

Phase shifting the bridge is something I'm not at all familiar with so I can't comment on that. (It sounds confusing, I need to see some oscilloscope shots)

Frequency shifting sounds like it might be challenging to find a good frequency ramp as davekni said, but it's worth experimenting I guess.

Cycle skip modulation also mentioned by davekni sounds like the most elegant way to me, although I can imagine it might be somewhat challenging to implement too. That way you should be able to preserve soft-switching. That's what I might want to try if I were to build a Tesla coil now. :o
« Last Edit: September 19, 2021, 11:13:54 PM by johnnyzoo »

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #4 on: September 20, 2021, 12:53:39 AM »
Quote
Cycle skip modulation also mentioned by davekni sounds like the most elegant way to me, although I can imagine it might be somewhat challenging to implement too. That way you should be able to preserve soft-switching. That's what I might want to try if I were to build a Tesla coil now.
This thread discusses unsucessful attempts at pulse-skip QCW control:
https://highvoltageforum.net/index.php?topic=292.msg1862#msg1862

However, this link shows QCW coils modulated to play music:
https://highvoltageforum.net/index.php?topic=472.msg2879#msg2879

If sword sparks can be generated while modulating enough for music, it seems like pulse-skip modulation could be of the same order.  Perhaps the issue is near ramp beginning when most pulses are being skipped.  That is where I hope to experiment eventually.  Perhaps start with phase-shift initially, then use pulse-skip later in each ramp for efficiency.

Quote
I'm not sure if I follow.. You need the PLL to lock at the resonant frequency of the primary so that the ramp will be closer and closer to the resonant frequency.
QCW coils generally run at the upper pole of  the dual-resonant system, not at the primary resonance.  The goal of open-loop drive is to start slightly higher frequency than the upper pole.  Higher to avoid coupling too much energy initially.  Then ramp the frequency lower to increase energy coupling.  As the arc grows, the now-loaded upper pole frequency will drop too.  This provides some negative feedback for stability.  The arc can grow only to the extent that the drive frequency is ramping down to keep feeding increasing energy.

I'm adding open loop frequency control to the experiment list for my eventual QCW coil.  (Will be a while.  Hand injury last April has prevented most construction, and will for coming months as I recover from surgery.)  If I get initial success with conventional phase-shift ramping, I'll measure the resulting frequency ramp, then try duplicating that frequency ramp open-loop.

PS:  Found this link to "Simple Driver" documentation.  Appendix A describes the version where phase-shift is between the two H-bridge halves:
https://tqfp.org/simple-tesla/simpledriver-v23-in-english.html
Here one half of the H-bridge runs in normal ZCS mode and the other half shifts from 180 to 0 degrees (where 0 refers to normal H-bridge phasing) during the ramp.

Does anyone have a phase-shift QCW coil where the entire H-bridge phase is shifted relative to current (90 to 0 degrees)?
« Last Edit: September 20, 2021, 02:33:22 AM by davekni »
David Knierim

Offline johnnyzoo

  • High Voltage Enthusiast
  • *
  • Posts: 27
  • Karma: +1/-0
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #5 on: September 20, 2021, 09:24:10 PM »
Quote
Cycle skip modulation also mentioned by davekni sounds like the most elegant way to me, although I can imagine it might be somewhat challenging to implement too. That way you should be able to preserve soft-switching. That's what I might want to try if I were to build a Tesla coil now.
This thread discusses unsucessful attempts at pulse-skip QCW control:
https://highvoltageforum.net/index.php?topic=292.msg1862#msg1862

However, this link shows QCW coils modulated to play music:
https://highvoltageforum.net/index.php?topic=472.msg2879#msg2879

If sword sparks can be generated while modulating enough for music, it seems like pulse-skip modulation could be of the same order.  Perhaps the issue is near ramp beginning when most pulses are being skipped.  That is where I hope to experiment eventually.  Perhaps start with phase-shift initially, then use pulse-skip later in each ramp for efficiency.



Interesting threads, thanks.

There was a link to an old thread on 4hv.org (https://4hv.org/e107_plugins/forum/forum_viewtopic.php?p=2&id=128784) and if I understood correctly on my quick read, that particular coil was configured to turn the bridge off during a skipped cycle which recycles primary energy into the DC bus.

How about shorting the primary instead, has anyone tried that? It would allow the primary to oscillate freely, like a spark gap coil does, and the current would decay slower.
edit: Freewheeling is mentioned in the thread that you linked, so I suppose it has been tried too.


I was also mentioned by the builder that the frequency might have been too low for sword style arcs, but I guess other people have tried higher frequencies?
« Last Edit: September 20, 2021, 09:37:25 PM by johnnyzoo »

Offline Uspring

  • High Voltage Engineer
  • ****
  • Posts: 253
  • Karma: +19/-0
  • Physicist
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #6 on: September 22, 2021, 07:21:12 PM »
Quote
QCW coils generally run at the upper pole of  the dual-resonant system, not at the primary resonance.  The goal of open-loop drive is to start slightly higher frequency than the upper pole.  Higher to avoid coupling too much energy initially.  Then ramp the frequency lower to increase energy coupling.  As the arc grows, the now-loaded upper pole frequency will drop too.  This provides some negative feedback for stability.  The arc can grow only to the extent that the drive frequency is ramping down to keep feeding increasing energy.

You have to be careful choosing tank parameters for this kind of operation. The arc load will not only shift the secondary resonance curve but will also widen it. That can cause a positive feedback leading to an unexpected power jump.
The dissipative part of the arc load will look like it will add a resistance into the primary tank. When you run, as in a typical coil, at a pole frequency, that added resistance will decrease primary current and will cause a negative feedback on power. There is no reactive part of the primary current.

When you run, as proposed, a considerable amount above the upper pole, then primary current will be mostly limited by the reactive impedance of the primary tank and not by the added resistance. When this resistance increases, e.g. due to arc load, then primary current won't be much affected by it. But that implies more input power, since current stays the same and resistance increases. And more input power will increase arc load.

Initially you have to run with mostly reactive primary current as this is the method to limit input power.

Quote
PS:  Found this link to "Simple Driver" documentation.  Appendix A describes the version where phase-shift is between the two H-bridge halves:
https://tqfp.org/simple-tesla/simpledriver-v23-in-english.html
Here one half of the H-bridge runs in normal ZCS mode and the other half shifts from 180 to 0 degrees (where 0 refers to normal H-bridge phasing) during the ramp.

An interesting side effect of this procedure is, that the phase between primary current and voltage is not anymore 0 degrees as in ZCS operation of both of the bridge halves. Therefore the coil is not generally run at a pole frequency anymore. Optimum ramp shapes probably differ for different signs of the bridge shift phase.

I wonder how sensitive sword arcs are to voltage ripples caused e.g. by cycle skipping. Steve Ward once showed me some data of his, where he started a QCW arc at 40kV and ended it at 55kV, when the arc had reached a length of 50+ inches. That amounted to a voltage rise of 15kV during about 5000 cycles. That is an increase of only 3 V per cycle. If this is really needed to keep an arc sword like, cycle skipping looks futile. Secondary Q is much too low to avoid a voltage drop even much larger than this.

Anyway, it would be interesting to see, if voltage ripples could be used to intentionally grow branches in a sword spark.

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #7 on: September 23, 2021, 06:15:34 AM »
Quote
When you run, as proposed, a considerable amount above the upper pole, then primary current will be mostly limited by the reactive impedance of the primary tank and not by the added resistance. When this resistance increases, e.g. due to arc load, then primary current won't be much affected by it. But that implies more input power, since current stays the same and resistance increases. And more input power will increase arc load.
Yes, more arc load will increase power, but will decrease secondary voltage.  So I don't see any positive feedback occurring.

Quote
An interesting side effect of this procedure is, that the phase between primary current and voltage is not anymore 0 degrees as in ZCS operation of both of the bridge halves. Therefore the coil is not generally run at a pole frequency anymore. Optimum ramp shapes probably differ for different signs of the bridge shift phase.
I'm hoping phase-shift QCW builders will offer information on their builds.  Exactly what is being shifted in phase relative to what else?  I'm guessing that most designs will cause frequency shift as well.  The only way I'm thinking of to avoid frequency shift is to adjust effective H-bridge pulse width while keeping pulses centered at current peaks.  Pulse width would presumably be adjusted by relative phase of the two H-bridge halves.  That keeps 50% duty cycle on each half-bridge.
Do you expect any issuesd due to frequency shift due to phase shift?  Shift would be small initially when Q is high.

Quote
I wonder how sensitive sword arcs are to voltage ripples caused e.g. by cycle skipping. Steve Ward once showed me some data of his, where he started a QCW arc at 40kV and ended it at 55kV, when the arc had reached a length of 50+ inches. That amounted to a voltage rise of 15kV during about 5000 cycles. That is an increase of only 3 V per cycle. If this is really needed to keep an arc sword like, cycle skipping looks futile. Secondary Q is much too low to avoid a voltage drop even much larger than this.
Yes, that is what I plan to experiment with eventually.  Given that buck-converter driven coils usually have buck frequency well below coil frequency, buck ripple voltage likely makes not-quite-monotonic coil voltage ramps.
David Knierim

Offline Netzpfuscher

  • High Voltage Technician
  • ***
  • Posts: 129
  • Karma: +11/-0
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #8 on: September 23, 2021, 08:49:51 AM »
On the UD3 one half of the bridge switches normally in zero crossing the other half is shifted from 0-180 deg. After each pulse the bridge switches to equalise thermal load. (Steve Ward design)

The ramp is arbitrary. I have a ~150µs interrupt in which I copy new phase shift values from a buffer to the logic. Ramps can be programmed with a few simple parameters, or with drawing functions (line x1 y1 x2 y2, ...)

I also have QCW MIDI and QCW SID support (In the newest synthesizer implementation I tossed the actual MIDI implementation but there is something better ;)) actually it is more a long pulse plus modulation, I simply synthesise a sound waveform and send it to the coil on a note on event, but without a ramp (but add a ramp should be easy)
The new synth is a block based synth from TMaxElectronics Midistick ported to the UD3. It has the nice feature to build a "instrument" on a graphically basis you can connect several blocks like ramps, sines, jumps, random.... if I add the qcw phase angle to the writable values its done. Then you can control phase angle, current and pulse length in realtime (1 ms resolution, I think I need a underlying buffer for faster events).

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #9 on: September 23, 2021, 05:46:38 PM »
Quote
On the UD3 one half of the bridge switches normally in zero crossing the other half is shifted from 0-180 deg. After each pulse the bridge switches to equalise thermal load. (Steve Ward design)
Thank you for the explanation.  That is the one version I'd seen so far, and what I'm planning to test first.
Anyone made a different version?
David Knierim

Offline Uspring

  • High Voltage Engineer
  • ****
  • Posts: 253
  • Karma: +19/-0
  • Physicist
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #10 on: September 23, 2021, 07:09:23 PM »
Quote
Yes, more arc load will increase power, but will decrease secondary voltage.  So I don't see any positive feedback occurring.

Here's an attempt to quantify my doubts:
Assume a voltage clamping effect of the arc. This is not quite true but Wards measurement of secondary voltage going from 40 kV to 55kV between breakout and full arc length is close to this.
In terms of output power (Pout = V^2/Rarc) this implies the proportionality Rarc ~ 1/Pout.
Put this in terms of secondary Q. Qsec ~ Rarc. So Qsec ~ 1/Pout.

Now I'm using the equation, which relates primary Q to secondary Q:

Qpri = (Qsec/k^2) * (1 - f^2/fsec^2)^2 + 1/(k^2 * Qsec),

where f is the operating frequency and fsec the secondary resonance frequency. In the case, that we are far off from resonance, the first term dominates and we get Qpri prpoportional to Qsec, i.e. Qpri ~ Qsec.
Power consumption in the primary tank is inversely proportional to Qpri. So we get:

Pinp ~ 1/Qpri, Qpri ~ Qsec and Qsec ~ 1/Pout or
Pout ~ Pinp

Pinp and Pout are, of course, the same on the average. But the above equation shows, that there is no additional constraint by the circuitry. So it might run at different power levels with no other parameter changed. That is a case of indifferent stability. I did neglect stabilising factors, i.e. the effect of detuning by resonance shift and the assumption of strict clamping, which is extreme. So basically I agree, that frequency control of the TC is stable but perhaps only marginally so, so that small changes in frequency might have occasionally big effects.

Quote
Do you expect any issues due to frequency shift due to phase shift?  Shift would be small initially when Q is high.

No, not really. Frequency dependence on phase angle becomes large, when Q is low. But then the phase shift due to bridge shifting is low, due to large duty cycles. It is difficult to answer, since it depends on how large the duty cycle is for a given Q.

Quote
Given that buck-converter driven coils usually have buck frequency well below coil frequency, buck ripple voltage likely makes not-quite-monotonic coil voltage ramps.

Secondary Q and particularly primary Q, which is often larger, provides for some filtering of buck ripple. I suspect, that branching of arcs depend mostly on the conditions near the tip. Sword arcs seem to branch there. An open question is, if a voltage ripple actually makes it to the tip. It will eventually, but there might be some filtering on the way. Possibly a sword arc needs a longer duration of overvolting to branch.

Quote
On the UD3 one half of the bridge switches normally in zero crossing the other half is shifted from 0-180 deg. After each pulse the bridge switches to equalise thermal load. (Steve Ward design)
Does that imply non equal pulse spacing for e.g. low duty cycles? That would seem like a mild form of pulse skipping.

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #11 on: September 23, 2021, 09:08:23 PM »
Quote
Power consumption in the primary tank is inversely proportional to Qpri.
That is true for a parallel-driven tank circuit.  Since DRSSTCs are series-driven, power is proportional to Q at resonance, not inversely.  Off-resonance, there will be a Q for maximum power, with lower power on either side.

Quote
On the UD3 one half of the bridge switches normally in zero crossing the other half is shifted from 0-180 deg. After each pulse the bridge switches to equalise thermal load. (Steve Ward design)
If I understand correctly, swapping is after each full cycle of primary current.  Every other cycle has reversed half-bridge drive.  To check my understanding, here's simulation output of primary current and H-bridge voltages near the start of a ramp (low net drive voltage):



Red is primary current, green is differential voltage across H-bridge, yellow and cyan are the two H-bridge outputs offset vertically to avoid overlap.

The circuit is just to generate waveforms, not anything real:



Each H-bridge transition occurs while driving current, avoiding diode recovery.  Half of the transitions are just before zero current for minimum loss.  The other half are at higher current, although still fairly low here since near the ramp start.

Is this what UD3 generates?  If not, can you please point me to UD3 waveforms?
« Last Edit: September 24, 2021, 01:59:17 AM by davekni »
David Knierim

Offline Netzpfuscher

  • High Voltage Technician
  • ***
  • Posts: 129
  • Karma: +11/-0
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #12 on: September 24, 2021, 07:26:30 AM »
Copied from the spec sheet:

Phase Shift Bridge Driving
For QCW operation, the UD3 can be commanded to operate as a phase shifted driver, where the phase shift controls the average applied voltage to the tank circuit and can be modulated.  The phase shifted output is sent alternately to each GDT so that each set of transistors will spend half their cycles as ZCS and half their cycles as hard-switched phase shifted drive.  The GDT waveform required to do this puts up to 2X the V-s (volt-second) stress on the GDT, therefore, GDTs used with phase shift drive should be tested down to ½ of the intended operating frequency to verify they do not saturate. 

QCW Test Mode
At this point, the GDT outputs can be scoped and you should see an in-phase GDT drive signal with a frequency as defined in config.start_freq.
Phase shift doesn’t happen until the feedback CT (which is CT1; CT2 is for the hall effect sensor and may be omitted) receives config.start_cycles number of cycles, after which it will begin phase shift drive from ~20deg or so. Note that 0 = no phase shift and 255 = 180deg shift. To test this, a test sine wave can be fed into the CT input to simulate this.



Above shows the GDT outputs (cyan and yellow) and purple (Ch1 - Ch2). A transition point happens where phase shift begins after the desired number of cycles. The drive will then also lock onto the feedback frequency. A good way to look at this intuitively to see the ‘duty cycle’ as the area of the purple signal. In the first few cycles which are normal drive, phase shift is 0 and duty cycle is 100%. Then phase shift begins and the area drops significantly, beginning around 20 degrees or so.





By the way, we are collecting ideas for a UD4. The psoc in the UD3 is nearly full and we can't implement more features in hardware. I think we make a design with a Smart Fusion 2 SOC complete digital (sample everything with a high speed ADC) The Smart Fusion has a Gbit MAC which is great for cheap fiber ethernet and with DDR3 interface we have enough memory for all fancy shit ^^

https://www.microsemi.com/product-directory/soc-fpgas/1692-smartfusion2

« Last Edit: September 24, 2021, 07:38:23 AM by Netzpfuscher »

Offline Uspring

  • High Voltage Engineer
  • ****
  • Posts: 253
  • Karma: +19/-0
  • Physicist
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #13 on: September 24, 2021, 05:37:56 PM »
Quote
Quote
Power consumption in the primary tank is inversely proportional to Qpri.

That is true for a parallel-driven tank circuit.  Since DRSSTCs are series-driven, power is proportional to Q at resonance, not inversely.  Off-resonance, there will be a Q for maximum power, with lower power on either side.

I was thinking of off resonance operation, since that is where this kind of frequency controlled coil would mostly operate. Off resonance, where tank impedance is dominantly reactive, power will be inversely proportional to Q.

Thank you to both davekni and Netzpfuscher for the illustration of the "balanced " hard switching mode.

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #14 on: September 25, 2021, 05:34:54 AM »
Quote
I was thinking of off resonance operation, since that is where this kind of frequency controlled coil would mostly operate. Off resonance, where tank impedance is dominantly reactive, power will be inversely proportional to Q.
For off-resonance, 1/Q is a valid approximation at high Q.  As Q decreases, power peaks, then drops, approximating proportional to Q at low Q.

I'm ignoring dual-resonance for simplicity.  An L/C tank circuit series-driven slightly above resonant frequency behaves like an AC current source shunted by a small capacitor of value 2 * C * delta_frequency / frequency.  At high Q (high resistance load), output voltage is roughly constant.  This is the case you are concerned about, fixed voltage source feeding fixed-voltage load.  However, as soon as the load R decreases or the load C increases, output voltage drops.  The source impedance is not zero or even that low.  Source impedance is capacitive.  So slight capacitive load current will decrease voltage faster than slight resistive load current.  At high load (lower impedance than 2 * C * delta_frequency / frequency), behavior becomes mostly the current source, so power decreases with increasing load (with decreasing Q).

Quote
Thank you to both davekni and Netzpfuscher for the illustration of the "balanced " hard switching mode.
Yes, thanks to Netzpfuscher for confirming my understanding of UD3 alternating phase-shift drive.  Helped greatly to see waveforms that match my simulation.  BTW, if those waveforms are in the documentation, I'm not finding the correct documentation link.
« Last Edit: September 25, 2021, 06:13:40 AM by davekni »
David Knierim

Offline Uspring

  • High Voltage Engineer
  • ****
  • Posts: 253
  • Karma: +19/-0
  • Physicist
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #15 on: September 25, 2021, 06:49:45 PM »
Quote
For off-resonance, 1/Q is a valid approximation at high Q.  As Q decreases, power peaks, then drops, approximating proportional to Q at low Q.

No disagreement here. It all depends on where we're at in the power versus Q curve. To get some numbers I've plotted the input resistance of a typical QCW coil. Blue is the real part and red the imaginary part. For a given primary current, the curves show the bridge input voltage, separated into a 0 and 90 degree shifted component relative to the input current.



Below is a zoomed version around the upper pole. In order to not input too much power into the coil initially, we would operate it at e.g. 400 kHz.



For a doubled arc load, the diagram looks like this:



The red curve is almost the same and the blue one doubles, but at 400kHz the total impedance hasn't changed much. That implies twice the power input if input voltage is kept constant.

When we then decrease frequency to increase current and power input, the max power will be achieved at the pole at about 370 kHz in the diagram. That is, where the red curve crosses 0. That is also the point, where Q and power become proportional. Proportionality or inverse proportionality depends on whether the reactive or the resistive part of the impedance is larger. Both conditions will occur during a rampup.
« Last Edit: September 25, 2021, 06:58:03 PM by Uspring »

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #16 on: September 25, 2021, 08:53:36 PM »
Agree, with high initial Q, double resistive load is does not reduce voltage much.  It is still a small load.

What does your QCW arc model say about arc current phase near the beginning.  I suspect it is more capacitive than resistive at that point, which would reduce voltage faster..

Hope to experiment with all this eventually, once my hand finally heals and I get caught up with other pending projects.
David Knierim

Offline Uspring

  • High Voltage Engineer
  • ****
  • Posts: 253
  • Karma: +19/-0
  • Physicist
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #17 on: September 27, 2021, 06:47:52 PM »
Quote
What does your QCW arc model say about arc current phase near the beginning.  I suspect it is more capacitive than resistive at that point, which would reduce voltage faster..

Early into the burst a simulation looks like this:
See below, strangely the forum software moves my inline images to the end.

The current is non sinusoidal due to extra breakdowns during the high voltage times of a cycle. That reduces phase shift. It is actually quite low. Later into the burst the current becomes sinusoidal and the phase shift settles at about 45 degrees.
But don't trust these simulations wrt to phase. AFAIK nobody has ever made an arc current measurement for a QCW coil. A reality check is sorely missing.

Quote
Hope to experiment with all this eventually, once my hand finally heals and I get caught up with other pending projects.

I wish your hand gets well quickly and fully.
« Last Edit: September 27, 2021, 06:54:49 PM by Uspring »

Offline davekni

  • High Voltage Expert
  • ******
  • Posts: 1324
  • Karma: +63/-0
  • Physicist, engineer (electronic), and hobbiest
    • View Profile
Re: Idea for QCW DRSSTC
« Reply #18 on: September 28, 2021, 04:30:28 AM »
Quote
The current is non sinusoidal due to extra breakdowns during the high voltage times of a cycle. That reduces phase shift. It is actually quite low. Later into the burst the current becomes sinusoidal and the phase shift settles at about 45 degrees.
Thank you for sharing simulation details.  Does indicate low (perhaps 20 degrees) phase shift.  If accurate, there would be weak negative feedback at the start with open-loop frequency ramping, likely making precise smooth control difficult (your initial thesis of this thread).

Quote
But don't trust these simulations wrt to phase. AFAIK nobody has ever made an arc current measurement for a QCW coil. A reality check is sorely missing.
Some day I hope to make such measurements with my fiber scope probe.  Need to build a QCW coil first.  Will also experiment with open-loop frequency ramping then.

Quote
I wish your hand gets well quickly and fully.
Thank you!
David Knierim

High Voltage Forum

Re: Idea for QCW DRSSTC
« Reply #18 on: September 28, 2021, 04:30:28 AM »

 


* Recent Topics and Posts

post Re: Mains Staccato / T-200 VTTC
[Vacuum Tube Tesla Coils (VTTC)]
304er
Today at 01:58:47 AM
post Re: Mains Staccato / SGTC
[Spark Gap Tesla Coils (SGTC)]
304er
October 24, 2021, 10:42:48 PM
post Re: My Bestest HV ZVS Driver and Jacobs Ladder
[Transformer (Ferrite Core)]
Duane B
October 24, 2021, 08:21:45 PM
post Re: Mains Staccato / T-200 VTTC
[Vacuum Tube Tesla Coils (VTTC)]
Duane B
October 24, 2021, 08:04:02 PM
post Re: Mains Staccato / SGTC
[Spark Gap Tesla Coils (SGTC)]
Duane B
October 24, 2021, 07:56:31 PM
post My Switches Don’t Switch
[Voltage Multipliers]
abstruse1
October 24, 2021, 06:50:05 PM
post Mains Staccato / T-200 VTTC
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 24, 2021, 11:18:22 AM
post Mains Staccato / SGTC
[Spark Gap Tesla Coils (SGTC)]
304er
October 24, 2021, 09:44:10 AM
post Some more VTTC controllers and SSR's being applied
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 24, 2021, 06:21:17 AM
post Re: My Bestest HV ZVS Driver and Jacobs Ladder
[Transformer (Ferrite Core)]
davekni
October 24, 2021, 05:55:33 AM
post VTTC Staccato/Interrupter Controller modified so SSR is useable for LShPS
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 24, 2021, 05:47:46 AM
post Re: My Bestest HV ZVS Driver and Jacobs Ladder
[Transformer (Ferrite Core)]
MRMILSTAR
October 24, 2021, 05:03:08 AM
post My Bestest HV ZVS Driver and Jacobs Ladder
[Transformer (Ferrite Core)]
Andrew321
October 24, 2021, 02:21:37 AM
post Re: Finally finalizing my 304er VTTC
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 23, 2021, 09:14:00 PM
post Re: Finally finalizing my 304er VTTC
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 23, 2021, 08:48:22 PM
post Re: Finally finalizing my 304er VTTC
[Vacuum Tube Tesla Coils (VTTC)]
Mads Barnkob
October 23, 2021, 08:33:22 PM
post Re: Finally finalizing my 304er VTTC
[Vacuum Tube Tesla Coils (VTTC)]
MRMILSTAR
October 23, 2021, 03:40:46 PM
post Re: Finally finalizing my 304er VTTC
[Vacuum Tube Tesla Coils (VTTC)]
304er
October 23, 2021, 10:29:37 AM
post Re: Battery powered DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
TMaxElectronics
October 23, 2021, 01:07:13 AM
post Re: DRSSTC tuning
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
October 23, 2021, 01:05:04 AM
post Re: Hi! 811 A tesa coil
[Vacuum Tube Tesla Coils (VTTC)]
Duane B
October 23, 2021, 12:48:40 AM
post Re: DRSSTC tuning
[Dual Resonant Solid State Tesla coils (DRSSTC)]
kubajed
October 23, 2021, 12:01:14 AM
post Re: Hi! 811 A tesa coil
[Vacuum Tube Tesla Coils (VTTC)]
jpvvv123
October 22, 2021, 11:52:23 PM
post UD3 CPL file for smt assembly by JLC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Franksmather
October 22, 2021, 08:56:59 PM
post Tesla Coil Show Controller - Analog Audio Interrupter and Test (Part 6 of 8)
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Mads Barnkob
October 22, 2021, 11:58:51 AM
post Re: Next Gen DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Netzpfuscher
October 22, 2021, 07:03:26 AM
post Re: Where to buy DIY or home made capacitor book(s)?
[Capacitor Banks]
Twospoons
October 22, 2021, 05:04:51 AM
post Re: Idea for increased electromagnetic coin shrinkage
[Capacitor Banks]
davekni
October 22, 2021, 04:43:23 AM
post Re: Where to buy DIY or home made capacitor book(s)?
[Capacitor Banks]
davekni
October 22, 2021, 04:27:13 AM
post Re: Where to buy DIY or home made capacitor book(s)?
[Capacitor Banks]
HVuser
October 21, 2021, 11:15:28 PM
post Re: Tesla Coil Music
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Intra
October 21, 2021, 09:45:55 PM
post Re: Coin shrinking video
[Capacitor Banks]
MRMILSTAR
October 21, 2021, 08:32:37 PM
post Re: Coin shrinking video
[Capacitor Banks]
klugesmith
October 21, 2021, 06:10:06 PM
post Re: 3kJ coin shrinking
[Capacitor Banks]
klugesmith
October 21, 2021, 06:09:19 PM
post Re: Idea for increased electromagnetic coin shrinkage
[Capacitor Banks]
klugesmith
October 21, 2021, 06:07:54 PM
post Re: Next Gen DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Intra
October 21, 2021, 01:27:29 PM
post Re: Interrupter frequency?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
GrantV
October 21, 2021, 12:37:00 PM
post Re: QCW problem with ZVS and phase lead
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
October 21, 2021, 06:34:26 AM
post Re: Idea for increased electromagnetic coin shrinkage
[Capacitor Banks]
davekni
October 21, 2021, 06:06:50 AM
post 3kJ coin shrinking
[Capacitor Banks]
davekni
October 21, 2021, 05:48:49 AM
post Re: Interrupter frequency?
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Kevindk9
October 21, 2021, 01:11:41 AM
post Re: Next Gen DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Kevindk9
October 21, 2021, 12:54:21 AM
post Idea for increased electromagnetic coin shrinkage
[Capacitor Banks]
MRMILSTAR
October 20, 2021, 09:31:01 PM
post Re: Battery powered DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Weston
October 20, 2021, 08:04:27 PM
post Re: Starting on first coil, Medium DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
AeraCura_
October 20, 2021, 05:23:00 PM
post Re: Starting on first coil, Medium DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Mads Barnkob
October 20, 2021, 01:22:22 PM
post Re: Battery powered DRSSTC
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Mads Barnkob
October 20, 2021, 01:14:06 PM
post Re: QCW problem with ZVS and phase lead
[Dual Resonant Solid State Tesla coils (DRSSTC)]
Vtroxi
October 20, 2021, 09:18:37 AM
post Re: QCW problem with ZVS and phase lead
[Dual Resonant Solid State Tesla coils (DRSSTC)]
davekni
October 20, 2021, 06:48:43 AM
post Coin shrinking video
[Capacitor Banks]
MRMILSTAR
October 20, 2021, 06:01:40 AM

Sitemap 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 
SimplePortal 2.3.6 © 2008-2014, SimplePortal