Why are SGT50T65FD1PN soo cheap on lcsc?

[Miki_407]

I was searching on lcsc when I found igbts misplaced into bjt section claiming to be able to do peak current of 150A in the datasheet. The price is just 0.981usd per piece if ordering 30+ pieces. I should say that I had no problems with SGT40N60NPFDPN from the same manufacturer at about the same price. My question is are these igbts a good option to buy for a drsstc?

Links:
Lcsc product: https://lcsc.com/product-detail/Bipolar-Transistors-BJT_Hangzhou-Silan-Microelectronics-SGT50T65FD1PN_C2761787.html
Datasheet translated using google translate: https://translate.google.com/translate?hl=en&sl=auto&tl=en&u=https%3A%2F%2Fdatasheet.lcsc.com%2Flcsc%2F2103191913_Hangzhou-Silan-Microelectronics-SGT50T65FD1PN_C2761787.pdf

If I missed any information I will provide it as soon as I can.

[Power-Max]

The thermal resistance is 0.53 K/W which is pretty bad IMHO. I got some ON semi 60N65 parts with a thermal resistance of 0.25 K/W. I've also seen TO-220 package devices with lower thermal resistances. This matters when you are dissipating a good deal of power due to hard switching or high RMS currents.

[Weston]

Interesting. First time I have seen Chinese IGBTs. I wonder how much of the IP is home grown...

The switching loss seems slightly high compared to some other IGBT datasheets I have looked at, but nothing that bad. And a DRSSTC gets close to zero current switching, so switching losses should be low anyways.

The thermal resistance of 0.53 K/W implies the die is relatively small, so pulsed power will be more limited. However, the datasheet has no plot of transient thermal impedance so you can not directly compare with other IGBTs.

As IGBT technology has improved the die size has become smaller, so most IGBTs on the market have a smaller die and worse tolerance for abuse than the IGBTs people were using 10 years ago or whatever.

Nothing about these IGBTs seems obviously bad. They should work ok in a small DRSSTC. At less than $1 a pop you might as well buy them and see how they work.

My biggest concern would be that the datasheet has more "optimistic" values than what people are typically used to.

[rikkitikkitavi]

The thermal resistance is 0.53 K/W which is pretty bad IMHO. I got some ON semi 60N65 parts with a thermal resistance of 0.25 K/W. I've also seen TO-220 package devices with lower thermal resistances. This matters when you are dissipating a good deal of power due to hard switching or high RMS currents.

Does it really matter, considering thermal transfer package to heatsink is limited , especially if you use some form of insulation and not just grease the surfaces?Even the attachment of the capsule has significance. Making the heatsink slightly larger so that the sum of thermal resistance stays the same is easy. 

Especially some manufacturers states ridicuosly high power capabilites based on theoretical calculations. I mean, 350W in a TO-220? Seriously?

But I say as previous, are the datasheets trustworthy?

[Steve Ward]

Does it really matter, considering thermal transfer package to heatsink is limited , especially if you use some form of insulation and not just grease the surfaces?Even the attachment of the capsule has significance. Making the heatsink slightly larger so that the sum of thermal resistance stays the same is easy.

Especially some manufacturers states ridicuosly high power capabilites based on theoretical calculations. I mean, 350W in a TO-220? Seriously?

This dissipation rating or Rth j-c is mostly indicative of how large the actual semiconductor is, so one with half the Rth (or 2X the Pdiss) is indeed about twice the area and consequently will have more volume to absorb the high power losses in pulsed applications.  The dissipation rating is obtained by assuming 25*C tab/interface temperature with Tjmax (150 or 175*C typically) applied to the junction and measuring the power flow from the chip, so its not a "practical use" rating, but still a reasonable metric to compare by. 

So even though the Rth of the device itself is only a small portion of the total thermal resistance stackup (typical TO-247 insulator might be ~1*C/W) the fact that its a bigger chip inside means it has lower transient thermal impedance and will handle greater pulse power.  Even for non-pulse power designs, it can really help to pick the biggest chip size for a given package to increase the power density of a design, and some designs really can appreciate the .2 to .5 *C/W reduction of going from a wimpy device to a strong one.

[Power-Max]

Does it really matter, considering thermal transfer package to heatsink is limited , especially if you use some form of insulation and not just grease the surfaces?Even the attachment of the capsule has significance. Making the heatsink slightly larger so that the sum of thermal resistance stays the same is easy.

Especially some manufacturers states ridicuosly high power capabilites based on theoretical calculations. I mean, 350W in a TO-220? Seriously?

This dissipation rating or Rth j-c is mostly indicative of how large the actual semiconductor is, so one with half the Rth (or 2X the Pdiss) is indeed about twice the area and consequently will have more volume to absorb the high power losses in pulsed applications.  The dissipation rating is obtained by assuming 25*C tab/interface temperature with Tjmax (150 or 175*C typically) applied to the junction and measuring the power flow from the chip, so its not a "practical use" rating, but still a reasonable metric to compare by. 

So even though the Rth of the device itself is only a small portion of the total thermal resistance stackup (typical TO-247 insulator might be ~1*C/W) the fact that its a bigger chip inside means it has lower transient thermal impedance and will handle greater pulse power.  Even for non-pulse power designs, it can really help to pick the biggest chip size for a given package to increase the power density of a design, and some designs really can appreciate the .2 to .5 *C/W reduction of going from a wimpy device to a strong one.

'
I agree 100%.

I have also found from experience that some PMOS transistors I have, tend to tolerate a bit more abuse than equally current-rated NMOS devices, I expect it's because NMOS has approx. 3 times better electron mobility which means the die size is physically smaller for the same current handling. Smaller die also means smaller parasitic capacitance. This is especailly true for GaN or SiC devices. If you pick one with the same current rating as the silicon one, the die will be smaller and not be as tolerant to abuse. The capacitance and gate charge figures are also reasonable metrics to go by when trying to judge die size. It would be nice if manufactures just straight up specified the thermal impedance rather than steady-state thermal resistance. I suppose they sort-of do in a roundabout way via the Safe Operating Area graph.

[rikkitikkitavi]

 
Good points from previous posts, thanks for that.

Does the thermal impedance really differ that much for shorter periods of time? What is the actual weight of a silicon die? 50-100mg ?
A chip with a load of 50W thermal (DC) how much does it matter when the load pulse is measured in Joules?

I have not done the math, or studied the thermal impedance curves (not so common in the datasheets) for different transistors. But I can imagine that doubling the die must mean some type of increased transient capacity even if not perhaps doubling is reachable due to other constrains like bonding wires popping like fuses ...

For sure a lot of R/D has been put into shrinking dies so that the semiconductors get more dies out of a wafer, which means more profit and hence they tend to have lower margin for abuse.

Atleast is cheaper to use two transistors than one to half the thermal resistance than a larger heatsink in most cases atleast for DC or low frequency applications (considering load share is equal) .But that is not really relevant in this case.

[Weston]

It would be nice if manufactures just straight up specified the thermal impedance rather than steady-state thermal resistance. I suppose they sort-of do in a roundabout way via the Safe Operating Area graph.

Most manufactures do provide this in the form of the transient thermal impedance plot. The Chinese IGBTs do not, but what do you expect from budget parts.

Here is a typical example:



The real challenge is then figuring out what the allowable delta T is. Even if you stay below the maximum junction temperature, repeated temperature cycling stresses the die attach material and can relatively quickly cause failure. The product literature on it is surprisingly spotty.

[Hydron]

Micross have a few datasheets for die-only IGBTs, for example the following:
https://shop.micross.com/pdf/fairchild/igbt/FGY75N60SM_IGBT_DIE.pdf
You could easily work out the volume and thus mass of the silicon from the measurements given (doping can be ignored, just use the specific gravity of pure silicon). Note that this particular IGBT is rather thin (I believe due to the technology used). The equivalent packaged (with diode die as well) is the FGY75N60SMD, so you can compare with the info and thermal impedance graphs from the packaged part datasheet.
The "60A" datasheet is also available (https://shop.micross.com/pdf/fairchild/igbt/FGA60N65SM_IGBT_DIE.pdf) - I believe that this is basically the die used in the famous FGH60N60SMD (it seems to be the 650V "FGA" version, but that datasheet is almost identical to the 600V "FGH" version other than the voltage rating, so I suspect it's the same or very similar die).

On another note, the die size specs above (and judicious use of a belt sander) were very useful in checking whether my very cheap Aliexpress FGY75N60SMD IGBTs were legit - I have a thread on this elsewhere on the boards (the short version was that the die size exactly matched and they also tested/worked fine).