Try to build the 4MHz ClassE SSTC

[NyaaX_X]

Hello everyone. I am trying to make the 4MHz SSTC. The famous one which use two stage ClassE topology seems more efficiency but the class E amplifier circuit is too hard to tune for me. And I saw Uzzors2k made a gate-driver driving one using NCP81074 form onsemi. So I tend to build that one first ~ I simulated the circuit on LTspice the driver IC I use a voltage source to approximate it. Maybe the simulation is not accurate? Please give me some advice while your free time ~ thanks. 

PS. And I am worrying about the gate-driver will getting hot. That is CW mode so. Maybe the GDT inductance can add to 4.36u for more one turn or 5.93u for more two turns each side.

#Richiburnett's HFSSTC https://www.richieburnett.co.uk/hfsstc.html
#Uzzors2k's HFSSTC http://uzzors2k.com/index.php?page=4MHzclassE1

#NCP81074 https://www.mouser.tw/datasheet/2/308/1/NCP81074_D-2317499.pdf
#Ferrite core https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/2577/TX20-10-7-4C65%20.pdf

[davekni]

PS. And I am worrying about the gate-driver will getting hot. That is CW mode so. Maybe the GDT inductance can add to 4.36u for more one turn or 5.93u for more two turns each side.

Yes, that is definitely a concern.  Might be OK with that driver chip and the total series inductance from driver to gate.  That may move enough power dissipation to FET internal gate resistance.  You can get some idea of power dissipation by probing power of the voltage source simulating the driver chip.  Hold "ALT" key down while clicking on that voltage source to make LTSpice plot power.

[NyaaX_X]

Thanks Dave !
Here I am simulating "your" style driver to drive it.

Please refer the attached file.

I don't know if I use that 15uH-33uF LC starting circuit will let the dual side Class E ZVS circuit fail to oscillate or it will fine cause I will using 16MHz Xtal feed into CD4024B ripple counter to get 4MHZ and sent the signal into the onsemi gate driver NCP81074 to drive the two "ZVS" mosfets. It seems luxury...

[davekni]

I don't know if I use that 15uH-33uF LC starting circuit will let the dual side Class E ZVS circuit fail to oscillate or it will fine cause I will using 16MHz Xtal feed into CD4024B ripple counter to get 4MHZ and sent the signal into the onsemi gate driver NCP81074 to drive the two "ZVS" mosfets. It seems luxury...

The ZVS circuit here is not an oscillator.  It is being controlled by FF outputs.

What is the purpose of 15nF C_g?  Is that a separate part?  Or intended to model IRFP460 Cgs?  If you have a reasonable Spice model for IRFP460, that model will include Cgs internally.

This ZVS gate drive isn't the only way to implement resonant gate drive.  Your initial driver chip circuit can be ran with a resonant load.  Requires same condition.  Total leakage inductance and added inductance between drive circuit and gate needs to resonate at 0.7x 4MHz operating frequency (sqrt(0.5)).  That way Vge will be the inverse of drive voltage and look like a sine wave.

There are disadvantages to resonant drive.  FET efficiency is better with more square gate waveform.  However, gate drive power dissipation is high with direct square wave drive.  That power can be partially dissipated in external gate series resistor to reduce driver chip dissipation.

[NyaaX_X]

15nF capacitor parallel to Irfp460A is acting as a tuning capacitor. I think that can be a part of resonant driver.

Cause I want to make the driver isolated from power stage and also separate them into two PCBs. And I want the driver works more efficiency. So I would choose the resonant driving. Also that is beautiful

But there is a question , I simulate the ZVS circuit and these Dual class E circuit and I saw thaat there is a huge power dissipation on the resonant capacitors and inductor. There voltage and current have like 90 degree phase shift so there is a lot of postive and negetive power on them. I don't know why, sorry for my shallow knowledge of it... There is a zip file of my simulation in the attached file earlier.

And why is resonant driving has less efficiency FET ? Maybe is that the FET is slower pass tbe linear zone than a fine square wave?

Thank you very much

[davekni]

But there is a question , I simulate the ZVS circuit and these Dual class E circuit and I saw thaat there is a huge power dissipation on the resonant capacitors and inductor. There voltage and current have like 90 degree phase shift so there is a lot of postive and negetive power on them.

Power is the rate of change of energy.  Inductors and capacitors store energy and give it back.  So power swings positive and negative.  On the simulation plot window, cntrl-click on a power plot.  That will display the average, which is all that matters for heat dissipation.  Make sure many cycles are displayed, or that an integer number of cycles, so that average will cancel cycle +/- parts.

And why is resonant driving has less efficiency FET ? Maybe is that the FET is slower pass tbe linear zone than a fine square wave?

Yes.

[NyaaX_X]

Oh my. That is the reactive power.I see. I was thinking that the voltage and current has same polarity is the real power... so the resistance part use real power and the inductance or capacitance use reactive power?

What? my secondary dissipating a hundred watt... Maybe the ESR of the secondary capacitance was setten to low.

[davekni]

I was thinking that the voltage and current has same polarity is the real power... so the resistance part use real power and the inductance or capacitance use reactive power?

Yes.

[NyaaX_X]

In the simulation. I think the power dissipation is too high in the driver now .. The IRFP460APBF allow + - 30V for Vgs. So the I push it to around 25V. Maybe I have to let the inductance of GDT more bigger to reduce the current flow. And tune the LC away from resonant frequency to increase the impedance to limit power ？

[davekni]

Maybe I have to let the inductance of GDT more bigger to reduce the current flow. And tune the LC away from resonant frequency to increase the impedance to limit power ？

Leakage inductance is what matters most for tuning.  That can be changed with either GDT inductance or GDT coupling factor.  Changing 15nF capacitor after GDT changes tuning too.

[NyaaX_X]

Yes I caculate the frequency with capacitance and the GDT inductance 1-k to approach resonant. But there are big inductance + small capacitance or small inductance + big capacitance choices to resonant and I think the second one will flow more current..

[NyaaX_X]

Hello~ I have a few new questions here.

01. I want to use the NCP81074A MOSFET gate-driver IC from ONSEMI to drive the IRFS4020 MOSFETs dual side "ZVS" class E driver. But in the data sheet I read that the IC have a "quasi" totem mosfet driver (If I connect the outH, outL) so I am worrying about the shoot-through of them. Which one is good for my circuit?
       

02. If I need to add the gate-resistor. Can I replace them with a high value of capacitor that like hundred times the Cgs? Or not. I am thinking of the heating issue and I will make the IC as near as possible to the MOSFETs. And in this case (totem MOSFET driver and 4Mega Hz) Do I need to add a quick turn off diode to the gate-resistor?

03. Do I need pull down resistors to MOSFETs? parallel to TVS diodes?

[davekni]

NCP81074A spec lists 10A peak reverse current for pulses.  So diodes are likely unnecessary.  If schottky diodes, could help since likely faster reverse recovery time than internal FET body diodes.

NCP81074A spec says nothing about requiring gate resistors.  I'd guess none is OK.

NCP81074A is very fast.  Look at all the spec layout recommendations carefully.

For your cap question, simulate it.

[NyaaX_X]

Thank you Dave for your reinforce 

l would place the IC as close as possible to the MOSFETs

And I also see other people place a pull down resistor to input + But I think there is a 200kohm internal resistor inside the IC
Is the external resistor needy for a logic D-flipflop IC signal in? I may use the https://www.digikey.tw/zh/products/detail/texas-instruments/SN74LVC2G74DCTR/484721 as the frequency divider.

Thank you again~

[NyaaX_X]

Hello, everybody.

Here I try to layout the PCB.
I think the copper pour may make some trouble...
The flipflop output wiring may have too much capacitance to GND or the too long path to gate-driver IC.
Any way, please help me to optimize the circuit~

[davekni]

May be fine as is.  Looks fairly good.
If I were tweaking this, I'd add three jumper wires in order to make back side continuous ground plane, except for the +12V rectangle at output end.  The two FF outputs could be jumper wires between existing via holes, removing those two back-side traces.  I'd also jumper +12V from near connector to output side.  That may be more useful, removing large cutout in back side ground.
I'd then add lots of vias between front and back ground planes, especially near bypass cap ground connections and chip ground pins.
Finally, I'd order this as a thin (~0.8mm) ECB to minimize inductance.

Good luck.

[NyaaX_X]

Thank you very much, Dave 

I edited it a little bit.

I wish I don't need jumper wire. So I keep the bottom trace of FF output. The copper pour GND and signal wires frame distance is 0.5mm.
The via I use through hole but not "via" so they are bigger but have metal cover the hole wall. Maybe I can add tin to them when soldering.

[davekni]

The front-to-back ground connections certainly help.  Probably fine.  Try it and see.

[NyaaX_X]

Sorry Dave,
I don't understand what do you mean.

I think I already put some via through hole on the board .. to connect the  GND on top and bottom layer

[davekni]

I think I already put some via through hole on the board .. to connect the  GND on top and bottom layer

Yes, that is what I said helps.